Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 12/04/2023
Public
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3.5.4.5.1. Example 5: Platform Designer Connection Flow

The following figures show how the Platform Designer System View and Address Map tabs display the connections and addressing in this Example 5.

For simplicity, the System View in the following figures applies the Hide Clocks and Resets filter.

Figure 41. Platform Designer Connection Flow—System View for Example 5


Figure 42. Platform Designer Connection Flow—Address Map for Example 5