Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 12/04/2023
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3.4.1.1. Connecting NoC IP and Assigning Base Addresses in the Platform Designer Connection Flow

This topic describes how to connect the NoC IP and assign base addresses using the Platform Designer connection flow, as NoC Design Flow Options describes. When using the Platform Designer connection flow, you must configure and instantiate your NoC IP in Platform Designer. The Platform Designer connection flow does not support instantiating the NoC IP in RTL.

Note: If you are using the NoC Assignment Editor connection flow, you can ignore this topic and refer instead to Connecting NoC IP and Assigning Base Addresses in the NoC Assignment Editor Connection Flow.

You can make NoC connections in Platform Designer using the AXI4 NoC manager, AXI4 NoC subordinate, HPS AXI4 NoC manager, and HPS AXI4 NoC subordinate interfaces in the System View tab.

AXI4 NoC manager interfaces are initiator interfaces of the fabric-facing NoC Initiator Intel FPGA IP. AXI NoC manager interfaces include initiator interfaces configured for AXI4 only, for AXI4-Lite only, or as shared AXI4 and AXI4-Lite. AXI NoC subordinate interfaces are the target interfaces of the High Bandwidth Memory (HBM2E) Interface Intel Agilex 7 FPGA IP, External Memory Interfaces (EMIF) IP, and the NoC Clock Control Intel FPGA IP. AXI NoC subordinate interfaces includes either AXI4 and AXI4-Lite target interfaces. AXI4 NoC manager interfaces can only connect to AXI4 NoC subordinate Interfaces.

HPS AXI4 NoC manager interfaces are the AXI4 initiator interfaces of the Hard Processor System Intel Agilex 7 / Agilex 9 FPGA IP. HPS AXI4 NoC subordinate interfaces are the AXI4 target interfaces of the External Memory Interfaces for HPS Intel FPGA IP. HPS AXI4 NoC manager interfaces can only connect to AXI4 NoC subordinate interfaces.

To connect the NoC IP and assign base addresses using the Platform Designer connection flow, follow these steps:

  1. In Platform Designer, configure and instantiate all the NoC IP in the System View tab.
  2. In the System View tab, connect the NoC IP to external pins or FPGA core logic, as appropriate for your application.
  3. In the System View tab, connect NoC initiators and targets for fabric-facing AXI4 managers by connecting the AXI4 NoC manager interfaces to the appropriate AXI4 NoC subordinate interfaces. Connect the NoC initiators and targets for HPS by connecting the HPS AXI4 NoC manager interface to the appropriate HPS AXI4 NoC subordinate interfaces.
    • AXI4 NoC manager interfaces on the fabric-facing NoC Initiator Intel FPGA IP must only connect to AXI4 NoC subordinate interfaces on memory resources for the fabric, such as High Bandwidth Memory (HBM2E) Interface Intel Agilex 7 FPGA IP or External Memory Interfaces (EMIF) IP, or to the AXI4 NoC subordinate port on the NoC Clock Control Intel FPGA IP to access NoC performance monitors.
    • HPS AXI4 NoC manager interfaces on Hard Processor System Intel Agilex 7 / Agilex 9 FPGA IP must only connect to HPS AXI4 NoC subordinate interfaces on memory resources for HPS in External Memory Interfaces for HPS Intel FPGA IP.
    Note: Connections between the AXI4 Lite NoC manager interface in the HPS MPFE and the AXI4 Lite NoC subordinate interfaces in the HPS-EMIF IP are hard-coded and not displayed in Platform Designer.
  4. Click the Address Map tab in Platform Designer to assign starting addresses for each AXI4 NoC interface connection. If an AXI4 NoC manager connects to multiple AXI4 NoC subordinate interfaces, ensure that each target has a unique starting address. You can specify these address mappings manually on the Address Map tab, or click System > Assign Base Addresses to allow Platform Designer to assign addresses automatically.
    Note: For NoC connections, you only need to specify the starting address. Specifying the ending address for NoC connections is unnecessary.
  5. Save the system and click Generate HDL. Platform Designer stores the NoC connectivity and addressing as assignments in the system .qip file. Platform Designer also generates the .inc file that also stores the connectivity and addressing.
    Note: The connections between AXI4 NoC manager and AXI4 NoC subordinate interfaces do not appear in the generated RTL. Similarly, the connections between HPS AXI4 NoC manager and HPS AXI4 NoC subordinate interfaces do not appear in the generated RTL.
  6. After you include the generated .inc file in your project, the design is now ready for RTL simulation. To proceed with compilation, first run Analysis & Elaboration and the proceed to Creating NoC Assignments for Compilation.