Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

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ID 768844
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Network-on-Chip (NoC) Overview 2. Hard Memory NoC in Intel Agilex® 7 M-Series FPGAs 3. NoC Design Flow in Intel® Quartus® Prime Pro Edition 4. NoC Real-time Performance Monitoring 5. Simulating NoC Designs 6. NoC Power Estimation 7. Hard Memory NoC IP Reference 8. Document Revision History of Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide
1. Network-on-Chip (NoC) Overview x
1.1. Introduction to Intel Agilex® 7 M-Series FPGAs 1.2. Terminology for Intel Agilex® 7 M-Series FPGAs 1.3. General NoC Architecture and Applications
1.3. General NoC Architecture and Applications x
1.3.1. General NoC Architecture 1.3.2. Example NoC Applications
1.3.2. Example NoC Applications x
1.3.2.1. Parallel Computing NoC Application 1.3.2.2. SmartNIC NoC Application
2. Hard Memory NoC in Intel Agilex® 7 M-Series FPGAs x
2.1. High-Level Architecture 2.2. NoC Segments 2.3. NoC Switch and Link Detail 2.4. Fabric NoC 2.5. NoC Protocol Support 2.6. NoC Design Considerations
2.2. NoC Segments x
2.2.1. UIB Segments 2.2.2. GPIO-B Segments 2.2.3. GPIO-B and HPS Segment 2.2.4. SDM Segment 2.2.5. PLL and SSM Segment
2.5. NoC Protocol Support x
2.5.1. AXI4 Protocol Support 2.5.2. AXI4 Handshaking Support 2.5.3. Quality of Service (QoS) Support 2.5.4. Transaction Ordering Support 2.5.5. AXI4-Lite Protocol Support
2.6. NoC Design Considerations x
2.6.1. Determining the Number of NoC Targets 2.6.2. Determining the Number of NoC Initiators 2.6.3. Fabric NoC Considerations 2.6.4. Latency Considerations 2.6.5. Initiator and Target Bandwidth Considerations 2.6.6. Horizontal Bandwidth Considerations 2.6.7. GPIO-B Bypass Mode and Initiators
3. NoC Design Flow in Intel® Quartus® Prime Pro Edition x
3.1. Hard Memory NoC Design Flow Overview 3.2. Using NoC Example Designs 3.3. NoC Building Blocks 3.4. Connecting NoC IP 3.5. Making NoC Logical Assignments 3.6. Making NoC Physical Assignments Using Interface Planner 3.7. Compiling the NoC Design
3.1. Hard Memory NoC Design Flow Overview x
3.1.1. NoC Design Flow Options
3.3. NoC Building Blocks x
3.3.1. NoC Initiators for Hard Processor Systems 3.3.2. NoC Targets for Hard Processor Systems 3.3.3. NoC Initiators for Fabric AXI4 Managers 3.3.4. NoC Targets for Fabric AXI4 Managers 3.3.5. NoC Clock Control
3.4. Connecting NoC IP x
3.4.1. General NoC IP Connectivity Guidelines 3.4.2. Connectivity Guidelines: NoC Initiators for Fabric AXI4 Managers 3.4.3. Connectivity Guidelines: NoC Targets for Fabric AXI4 Managers 3.4.4. Connectivity Guidelines: NoC Clock Control 3.4.5. Connectivity Guidelines: NoC Initiators for HPS 3.4.6. Connectivity Guidelines: NoC Targets for HPS
3.4.1. General NoC IP Connectivity Guidelines x
3.4.1.1. Connecting NoC IP and Assigning Base Addresses in the Platform Designer Connection Flow 3.4.1.2. Connecting NoC IP and Assigning Base Addresses in the NoC Assignment Editor Connection Flow
3.5. Making NoC Logical Assignments x
3.5.1. Creating NoC Assignments for Compilation 3.5.2. Using the NoC Assignment Editor 3.5.3. Troubleshooting NoC Assignment Editor 3.5.4. NoC Connection and Addressing Examples
3.5.2. Using the NoC Assignment Editor x
3.5.2.1. Step 1: Make Group Assignments in the NoC Assignment Editor 3.5.2.2. Step 2: Make Connection Assignments in the NoC Assignment Editor 3.5.2.3. Step 3: Make Attribute Assignments in the NoC Assignment Editor 3.5.2.4. Step 4: Validate Logical NoC Assignments and Generate Simulation File
3.5.4. NoC Connection and Addressing Examples x
3.5.4.1. Example 1: External Memory Interface with 1 AXI4 Initiator and 1 AXI4-Lite Initiator 3.5.4.2. Example 2: Two External Memory Interfaces with One AXI4 Initiator and One AXI4-Lite Initiator 3.5.4.3. Example 3: One External Memory Interfaces with Two AXI4 Initiators and One AXI4-Lite Initiator 3.5.4.4. Example 4: Two High-Bandwidth Memory Pseudo-Channels with Two AXI4 Initiators (Crossbar) and Shared AXI4-Lite Initiator 3.5.4.5. Example 5: Hard Processor System with Two External Memory Interfaces
3.5.4.1. Example 1: External Memory Interface with 1 AXI4 Initiator and 1 AXI4-Lite Initiator x
3.5.4.1.1. Example 1: Platform Designer Connection Flow 3.5.4.1.2. Example 1: NoC Assignment Editor Connection Flow
3.5.4.2. Example 2: Two External Memory Interfaces with One AXI4 Initiator and One AXI4-Lite Initiator x
3.5.4.2.1. Example 2: Platform Designer Connection Flow 3.5.4.2.2. Example 2: NoC Assignment Editor Connection Flow
3.5.4.3. Example 3: One External Memory Interfaces with Two AXI4 Initiators and One AXI4-Lite Initiator x
3.5.4.3.1. Example 3: Platform Designer Connection Flow 3.5.4.3.2. Example 3: NoC Assignment Editor Connection Flow
3.5.4.4. Example 4: Two High-Bandwidth Memory Pseudo-Channels with Two AXI4 Initiators (Crossbar) and Shared AXI4-Lite Initiator x
3.5.4.4.1. Example 4: Platform Designer Connection Flow 3.5.4.4.2. Example 4: NoC Assignment Editor Connection Flow
3.5.4.5. Example 5: Hard Processor System with Two External Memory Interfaces x
3.5.4.5.1. Example 5: Platform Designer Connection Flow 3.5.4.5.2. Example 5: NoC Assignment Editor Connection Flow
3.6. Making NoC Physical Assignments Using Interface Planner x
3.6.1. Using Interface Planner 3.6.2. Recommended Placement Order for NoC Elements in Interface Planner 3.6.3. Hard Memory NoC Locations in Interface Planner 3.6.4. NoC Performance Reports in Interface Planner
3.7. Compiling the NoC Design x
3.7.1. Fitter NoC Reports 3.7.2. Viewing NoC Elements in Chip Planner
5. Simulating NoC Designs x
5.1. Generating a Simulation Registration Include File (Platform Designer Connection Flow) 5.2. Generating a Simulation Registration Include File (NoC Assignment Editor Connection Flow) 5.3. Contents of Simulation Registration Include File
6. NoC Power Estimation x
6.1. Using the Intel FPGA PTC to Estimate NoC Power
7. Hard Memory NoC IP Reference x
7.1. NoC Initiator Intel FPGA IP 7.2. NoC Clock Control Intel FPGA IP
7.1. NoC Initiator Intel FPGA IP x
7.1.1. NoC Initiator Intel FPGA IP Parameters 7.1.2. NoC Initiator Intel FPGA IP Interfaces
7.1.2. NoC Initiator Intel FPGA IP Interfaces x
7.1.2.1. NoC Initiator Intel FPGA IP AXI4/AXI4-Lite Interfaces 7.1.2.2. NoC Initiator AXI4 User Interface Signals 7.1.2.3. NoC Initiator Intel FPGA IP AXI4-Lite User Interface Signals 7.1.2.4. NoC Initiator Intel FPGA IP Clock and Reset Signals 7.1.2.5. NoC Initiator Intel FPGA IP Platform Designer-Only Signals
7.2. NoC Clock Control Intel FPGA IP x
7.2.1. NoC Clock Control Intel FPGA IP Parameters 7.2.2. NoC Clock Control Intel FPGA IP Interfaces 7.2.3. NoC Clock Control Intel FPGA IP Platform Designer-only Signals
Answers to Top FAQs
1. Network-on-Chip (NoC) Overview
2. Hard Memory NoC in Intel Agilex® 7 M-Series FPGAs
3. NoC Design Flow in Intel® Quartus® Prime Pro Edition
4. NoC Real-time Performance Monitoring
5. Simulating NoC Designs
6. NoC Power Estimation
7. Hard Memory NoC IP Reference
8. Document Revision History of Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

3.4.1.1. Connecting NoC IP and Assigning Base Addresses in the Platform Designer Connection Flow

This topic describes how to connect the NoC IP and assign base addresses using the Platform Designer connection flow, as NoC Design Flow Options describes. When using the Platform Designer connection flow, you must configure and instantiate your NoC IP in Platform Designer. The Platform Designer connection flow does not support instantiating the NoC IP in RTL.

Note: If you are using the NoC Assignment Editor connection flow, you can ignore this topic and refer instead to Connecting NoC IP and Assigning Base Addresses in the NoC Assignment Editor Connection Flow.

You can make NoC connections in Platform Designer using the AXI4 NoC manager, AXI4 NoC subordinate, HPS AXI4 NoC manager, and HPS AXI4 NoC subordinate interfaces in the System View tab.

AXI4 NoC manager interfaces are initiator interfaces of the fabric-facing NoC Initiator Intel FPGA IP. AXI NoC manager interfaces include initiator interfaces configured for AXI4 only, for AXI4-Lite only, or as shared AXI4 and AXI4-Lite. AXI NoC subordinate interfaces are the target interfaces of the High Bandwidth Memory (HBM2E) Interface Intel Agilex 7 FPGA IP, External Memory Interfaces (EMIF) IP, and the NoC Clock Control Intel FPGA IP. AXI NoC subordinate interfaces includes either AXI4 and AXI4-Lite target interfaces. AXI4 NoC manager interfaces can only connect to AXI4 NoC subordinate Interfaces.

HPS AXI4 NoC manager interfaces are the AXI4 initiator interfaces of the Hard Processor System Intel Agilex 7 / Agilex 9 FPGA IP. HPS AXI4 NoC subordinate interfaces are the AXI4 target interfaces of the External Memory Interfaces for HPS Intel FPGA IP. HPS AXI4 NoC manager interfaces can only connect to AXI4 NoC subordinate interfaces.

To connect the NoC IP and assign base addresses using the Platform Designer connection flow, follow these steps:

  1. In Platform Designer, configure and instantiate all the NoC IP in the System View tab.
  2. In the System View tab, connect the NoC IP to external pins or FPGA core logic, as appropriate for your application.
  3. In the System View tab, connect NoC initiators and targets for fabric-facing AXI4 managers by connecting the AXI4 NoC manager interfaces to the appropriate AXI4 NoC subordinate interfaces. Connect the NoC initiators and targets for HPS by connecting the HPS AXI4 NoC manager interface to the appropriate HPS AXI4 NoC subordinate interfaces.
    • AXI4 NoC manager interfaces on the fabric-facing NoC Initiator Intel FPGA IP must only connect to AXI4 NoC subordinate interfaces on memory resources for the fabric, such as High Bandwidth Memory (HBM2E) Interface Intel Agilex 7 FPGA IP or External Memory Interfaces (EMIF) IP, or to the AXI4 NoC subordinate port on the NoC Clock Control Intel FPGA IP to access NoC performance monitors.
    • HPS AXI4 NoC manager interfaces on Hard Processor System Intel Agilex 7 / Agilex 9 FPGA IP must only connect to HPS AXI4 NoC subordinate interfaces on memory resources for HPS in External Memory Interfaces for HPS Intel FPGA IP.
    Note: Connections between the AXI4 Lite NoC manager interface in the HPS MPFE and the AXI4 Lite NoC subordinate interfaces in the HPS-EMIF IP are hard-coded and not displayed in Platform Designer.
  4. Click the Address Map tab in Platform Designer to assign starting addresses for each AXI4 NoC interface connection. If an AXI4 NoC manager connects to multiple AXI4 NoC subordinate interfaces, ensure that each target has a unique starting address. You can specify these address mappings manually on the Address Map tab, or click System > Assign Base Addresses to allow Platform Designer to assign addresses automatically.
    Note: For NoC connections, you only need to specify the starting address. Specifying the ending address for NoC connections is unnecessary.
  5. Save the system and click Generate HDL. Platform Designer stores the NoC connectivity and addressing as assignments in the system .qip file. Platform Designer also generates the .inc file that also stores the connectivity and addressing.
    Note: The connections between AXI4 NoC manager and AXI4 NoC subordinate interfaces do not appear in the generated RTL. Similarly, the connections between HPS AXI4 NoC manager and HPS AXI4 NoC subordinate interfaces do not appear in the generated RTL.
  6. After you include the generated .inc file in your project, the design is now ready for RTL simulation. To proceed with compilation, first run Analysis & Elaboration and the proceed to Creating NoC Assignments for Compilation.
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