5.1. Generating a Simulation Registration Include File (Platform Designer Connection Flow)
To generate a simulation registration include file in the Platform Designer connection flow, follow these steps:
- Connect the AXI4 NoC manager ports to the AXI4 NoC subordinate ports in the System View tab of Platform Designer. The AXI4 NoC manager ports are on the NoC Initiator Intel FPGA IP. The AXI4 NoC subordinate ports are on the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP and on the External Memory Interfaces (EMIF) IP.
- Click the Address Map tab in Platform Designer to assign base addresses for each NoC initiator to target connection. If an initiator connects to multiple targets, ensure that each target has a unique starting address. For NoC connections, you only need to specify the starting address. Specifying the ending address for NoC connections is unnecessary.
For HBM2e memory, the minimum address span is 1 GB and you must align base addresses to 1 GB boundaries. For external memory interfaces, the minimum address span is 4 GB and you must align base addresses to 4 GB boundaries. For example, if an initiator connects to both HBM2e memory and DDR5 memory, you can specify the base address for the HBM2e memory as 0x00000000, and specify the base address for the DDR5 memory as 0x40000000, assuming a 16 GB HBM2e memory space.
- Save the system and click Generate HDL. Platform Designer generates the registration include file along with the HDL. There is no need to run Intel Quartus Prime Analysis & Elaboration before simulation when using this flow.