Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 12/04/2023
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3.5.4.5. Example 5: Hard Processor System with Two External Memory Interfaces

Example 5 represents a Hard Processor System Intel Agilex 7 / Agilex 9 FPGA IP with a dual-channel NoC interface configuration. This configuration enables both HPS AXI4 NoC manager interfaces on the MPFE.

Example 5 also contains an instance of External Memory Interfaces for HPS Intel FPGA IP configured with two HPS AXI NoC subordinate ports. Both manager interfaces on the MPFE are connected to both HPS AXI NoC subordinate ports in a crossbar configuration. Each MPFE manager uses 0x0_0000_0000 as the base address for the first HPS AXI NoC subordinate port, and 0x2_0000_0000 as the base address for the second HPS AXI NoC subordinate port.

Example 5 also contains one instance of the NoC Clock Control Intel FPGA IP, but its AXI4 Lite interface is unconnected.