Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 12/04/2023
Public
Document Table of Contents
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2.6.4. Latency Considerations

You must consider the impact of latency when choosing locations for NoC initiators and NoC targets. The hard memory NoC consists of a horizontal array of switches that you attach to initiators and targets, as the diagrams in NoC Segments show.

Transactions between an initiator and target that are far apart laterally must transfer through many switches, increasing the minimum latency. Transactions between initiators and targets that connect to the same switch have the lowest latency. Figure 13. Horizontal Link Allocation for Top-Edge NoC and Figure 14. Horizontal Link Allocation for Bottom-Edge NoC show initiators and targets that connect to the same switch designated with Local connections.