E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 12/11/2021
Document Table of Contents Running the Simulation with New HEX File

If you modify the C-code design example simulation source files, you must generate a .HEX file using Nios® II Software Build Tools (SBT) for Eclipse.
  1. In the Intel® Quartus® Prime Pro Edition software, select Tools > Nios II Software Build Tools for Eclipse.
  2. Create a new workspace when the Workspace Launcher window prompt appears. Click OK to open the workspace.
  3. In the Nios II - Eclipse window, select File > New > Nios II Application and BSP from Template. A Nios II Application and BSP from Template appears.
  4. In the Nios II Application and BSP from Template window, fill in the following information:
    • For SOPC Information File name, browse to <design_example_dir>/hardware_test_design/nios_system and open the SOPC Information File (nios_system.sopcinfo) for your design. Click OK to select the file and Eclipse automatically loads all CPU settings.
    • For Project name, specify your desired project name. This example uses dynamic_reconfiguration_simulation.
  5. Click Finish to generate the project. The Intel® Quartus® Prime Pro Edition software creates a new directory named software in the specified project location.
  6. Replace the C-code source files located in your new software directory ( <design_example_dir>/hardware_test_design/software/dynamic_reconfiguration_simulation) with the following C-code source files from the <design_example_dir>/software/dynamic_reconfiguration_sim design:
    • c3_reconfig.c
    • c3_reconfig.h
    • c3_function.c
    • flow.c
    • main.c
    • packet_gen.c
    • packet_gen.h
      Note: The packet_gen.c and packet_gen.h files are only applicable for Ethernet dynamic reconfiguration (DR) design example and Ethernet to CPRI DR design example variants.
  7. In the Nios II - Eclipse window, press F5 or right-click your project and select Refresh to refresh the window and reload the new files into the project.
  8. On the Project Explorer view, right-click the dynamic_reconfiguration_simulation and select Build Project. Ensure the dynamic_reconfiguration_simulation.elf file is generated in the new <design_example_dir>/hardware_test_design/software/dynamic_reconfiguration_simulation directory.
  9. To generate a new HEX file, right-click the dynamic_reconfiguration_simulation in the Project Explorer view, point to Make Targets and select Build. A Make Targets dialog box appears.
  10. In the Make Targets dialog box, select mem_init_generate.
  11. Click Build. The mem_init_generate creates the new HEX (nios_system_onchip_memory2_0_onchip_memory2_0.hex) file. The new HEX file resides in the <design_example_dir>/hardware_test_design/software/dynamic_reconfiguration_simulation/mem_init directory.

Follow these steps to simulate the testbench:

  1. Open the <simulator_name>_files.tcl script in the <design_example_dir>/example_testbench/setup_scripts/common directory.
  2. Edit the TCL script to change the existing nios_system_onchip_memory2_0_onchip_memory2_0.hex file directory to the new HEX file generated from the Nios® II SBT for Eclipse:
    For example, change the following line in the TCL script from:
    lappend memory_files "[normalize_path "$QSYS_SIMDIR/../<design_example_dir>/hardware_test_design/ip/nios_system/nios_system_onchip_memory2_0/altera_avalon_onchip_memory2_191/sim/nios_system_onchip_memory2_0_onchip_memory2_0.hex"]"
    lappend memory_files "[normalize_path "$QSYS_SIMDIR/../<design_example_dir>/hardware_test_design/software/dynamic_reconfiguration_simulation/mem_init/nios_system_onchip_memory2_0_onchip_memory2_0.hex"]"
  3. Using the supported simulator of your choice, change to the testbench simulation directory to <design_example_dir>/example_testbench/ <simulator_name>.
  4. Run the simulation script for the simulator. The script compiles and runs the testbench in the simulator. Refer to .
  5. Analyze the results. The successful testbench performs the DR operations, sends and transmits packets for each DR operation, and displays "Nios has completed its transactions" and "Simulation PASSED" after completing the simulation.
    Note: For Nios® II-based testbench, the simulation runs for more than 5 hours.

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