E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 12/11/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.4.1.1. Clocking Scheme

Figure 37. Clocking Scheme for 24G CPRI with RS-FEC Dynamic Reconfiguration Design Example
Figure 38. Clocking Scheme for 9.8G CPRI Dynamic Reconfiguration Design Example

Did you find the information on this page useful?

Characters remaining:

Feedback Message