E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 12/11/2021
Public

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Document Table of Contents

4.6. Document Revision History for the E-tile Dynamic Reconfiguration Design Example

Document Version Intel® Quartus® Prime Version IP Version Changes
2021.12.11 21.3 20.2.0
  • Added support for Questa simulator.
  • Removed support for NCSim simulator.
  • Added new sections:
    • Dynamic Reconfiguration Flow for 25GbE PTP FEC to 25GbE PTP Non-FEC
    • Dynamic Reconfiguration Flow for 24G CPRI FEC to 24G CPRI Non-FEC
    • Dynamic Reconfiguration Flow for 25GbE PTP FEC to 24G CPRI FEC
    • Steps to Enable FEC
    • Steps to Disable FEC
2020.06.29 20.2 20.2.0
  • Added support for dynamic reconfiguration (DR) transitions from high speed CPRI protocol to low PMA-D modes in 25G Ethernet to CPRI Dynamic Reconfiguration Design Example:
    • 24G CPRI with RS-FEC to 10G CPRI
    • 10G CPRI to 9.8G CPRI
    • 9.8G CPRI to 4.9G CPRI
    • 4.9G CPRI to 2.4G CPRI
    • 2.4G CPRI to 24G CPRI with RS-FEC

    Updated DR simulation test sequence and DR hardware test GUI display with the added transitions.

  • Added dl_reset signal in the CPRI PHY Soft Registers table. The reset acts as a soft reset to the deterministic latency block.
2020.04.13 20.1 19.2.0
  • Added support for deterministic latency feature in the 25G Ethernet to CPRI protocol.
    • Updated the Clocking Scheme for 24G CPRI with RS-FEC Dynamic Reconfiguration Design Example figure.
    • Updated the Simulation Block Diagram for 25G Ethernet to CPRI Dynamic Reconfiguration Design Example figure.
    • Updated components described in the 25GE MAC+PCS with RS-FEC and PTP to CPRI Hardware Dynamic Reconfiguration Design Example Components section.
    • Added CPRI PHY soft registers table in the 25G Ethernet to CPRI Design Examples Registers section.
  • Updated Clock Control frequency setting in the Testing the E-tile Dynamic Reconfiguration Hardware Design Example section. This setting applies to CPRI and Ethernet to CPRI protocols.
  • Updated TEST_MODE selection in the 10GE/25GE MAC+PCS with RS-FEC Simulation Dynamic Reconfiguration Design Example Components section. TEST_MODE options are 0, 1, and 2.
2019.12.30 19.4 19.4.0
  • Added new PMA adaptation flow for 10G/25G variant.
  • Added simulation, compilation, and hardware support for Intel® Agilex™ dynamic reconfiguration design examples for CPRI protocols:
    • 24G CPRI with RS-FEC
    • 9.8G CPRI with RS-FEC
  • Added simulation, compilation, and hardware support for Intel® Agilex™ dynamic reconfiguration design examples for 100G Ethernet protocol
2019.10.18 19.3 19.3.0 Initial release.

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