E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 12/11/2021
Public
Document Table of Contents

2.3.2.3. 100GE PCS with Optional RS-FEC Hardware Design Example Components

Figure 20. 100GE MAC + PCS with Optional RS-FEC Hardware Design Example High Level Block Diagram
The E-tile Ethernet IP for Intel Agilex FPGA hardware design example includes the following components:
  • E-tile Ethernet IP for Intel Agilex FPGA core.
  • PCS packet generator and checker that coordinates the programming of the IP core, packet generation, and verify the packets.
  • IOPLL to generate a 100 MHz clock from a 50 MHz input clock to the hardware design example.
  • JTAG controller that communicates with the System Console. You communicate with the client logic through the System Console.

The hardware design example test initiates media-independent interface (MII) packet transmission from packet generator to the IP core. The packet generator supports incremental packet mode, fixed-size packet mode, and random packet content mode. Once reset is completed, the packet generator generates the number of packets requested to the IP core. The IP core transfers the packets through internal PMA loopback to the packet generator and checker for verification. This test only works with internal PMA loopback mode.

The following sample output illustrates a successful hardware test run for 100GE, PCS only with (528,514) RS-FEC variation:
% pcs_only_traffic_test
Running pcs_only_traffic_test test
 RX PHY Register Access: Checking Clock Frequencies (KHz) 

	REFCLK 		:2 (KHZ) 
	TXCLK 		:40284  (KHZ) 
	RXCLK 		:40284  (KHZ) 
	TXRSCLK 	:0  (KHZ) 
	RXRSCLK 	:0  (KHZ) 
 RX PHY Status Polling 
 Rx Frequency Lock Status     0x0000000f 
 Mac Clock in OK Condition?   0x00000001 
 Rx Frame Error               0x00000000
Rx PHY Fully Aligned?        0x00000001 
 Rx AM LOCK Condition?        0x00000001 
 Rx Lanes Deskewed Condition? 0x00000001 
Setting Number of frames to 6767
Setting Size of frames to 8588
Setting Size of frames to constant
-------------------------------------
PCS TRAFFIC = 0
pcs_only_traffic_test:pass
0
The following sample output illustrates a successful hardware test run for 100GE, PCS only with (544,512) RS-FEC variations:
% % pcs_only_traffic_test_pam4
Running pcs_only_traffic_test_pam4 test
RX PHY Register Access: Checking Clock Frequencies (KHz) 
	REFCLK 		:1 (KHZ) 
	TXCLK 		:41504  (KHZ) 
	RXCLK 		:41505  (KHZ) 
	TXRSCLK 	:0  (KHZ) 
	RXRSCLK 	:0  (KHZ) 
 RX PHY Status Polling 
 Rx Frequency Lock Status     0x0000000f 
 Mac Clock in OK Condition?   0x00000001 
 Rx Frame Error               0x00000000 
 Rx AM LOCK Condition?        0x00000001 
 Rx Lanes Deskewed Condition? 0x00000001 
-------------------------------------
PCS TRAFFIC = 0
Setting Number of frames to 5340
Setting Size of frames to 635
Setting Size of frames to random
pcs_only_traffic_test_pam4:pass

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