E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 12/11/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.4.5. CPRI Design Example Registers

Table 41.   E-tile CPRI PHY Intel® FPGA IP Hardware Design Example Register Map

Word Offset

Register Category

0x000000 – 0x000FFF CPRI PCS registers
0x010000 – 0x0107FF RS-FEC configuration registers
0x100000 – 0x1FFFFF Transceiver registers

Did you find the information on this page useful?

Characters remaining:

Feedback Message