E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 12/11/2021
Public

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3.1.7. Testing the E-tile CPRI PHY Intel® FPGA IP Hardware Design Example

After you compile the E-tile CPRI PHY Intel® FPGA IP core design example and configure it on your Intel® Agilex™ device, you can use the System Console to program the IP core and its embedded Native PHY IP core registers.

To turn on the System Console and test the hardware design example, follow these steps:

  1. After the hardware design example is configured on the Intel® Agilex™ device, in the Intel® Quartus® Prime Pro Edition software, on the Tools menu, click System Debugging Tools > System Console.
  2. In the Tcl Console pane, type cd hwtest to change directory to <design_example_dir>/hardware_test_design/hwtest_sl.
  3. Type source main_script.tcl to open a connection to the JTAG master and start the test.

    You can program the IP core with the following design example commands:

    The following sample output illustrates a successful test run for 24.33024 Gbps CPRI line bit rate with 1 CPRI channel:
    Info: Number of Channels = 1
    Info: JTAG Port ID       = 1
    Info: Speed              = 24G
    
    Info: Start of c3_cpri_test 
    
    INFO: Basic CPRI test 
    
    INFO: Checking PLL lock status...
    	iopll_sclk_locked 1, channel_pll_locked 1
    INFO: PLL is locked
    
    Loop 0
    INFO: Set Reconfig Reset
    INFO: Channel 0: Set CSR Reset
    INFO: Channel 0: Set TX Reset
    INFO: Channel 0: Set RX Reset
    INFO: Release Reconfig Reset
    INFO: Channel 0: Release CSR Reset
    INFO: Channel 0: Release TX Reset
    INFO: Channel 0: Release RX Reset
    INFO: Wait for master channel to stable
    INFO: Release Reset Done!
    INFO: Turn on serial loopback
    
    	INFO: Start of C3 ELANE XCVR Channel 0 Loopback mode
    
    	INFO: Polling For PMA Register: Read  XCVR CSR Register offset = 0x8a, data = 0x80 
    	INFO: Polling For PMA Register: Read  XCVR CSR Register offset = 0x8b, data = 0x8e 
    
    	INFO: C3 ELANE XCVR Channel 0 Loopback mode is successfully enabled 
    
    INFO: Running calibration...
    INFO: Channel 0 
    
    INFO: Assert TX RX Digital Reset 
    
    INFO: Channel 0: Set TX Reset
    INFO: Channel 0: Set RX Reset
    INFO: Reset PMA 
    
    	INFO: Waiting PMA reset . . .
    	INFO: Waiting 3
    	INFO: Waiting 4
    	INFO: Waiting 5
    	INFO: Waiting 6
    	INFO: Waiting 8
    	INFO: Waiting 9
    	INFO: Waiting 11
    	INFO: Waiting 12
    	INFO: Waiting 13
    
    INFO: De-assert TX Digital Reset 
    
    INFO: Channel 0: Release TX Reset
    	INFO: Internal loopback 
    
    
    	INFO: Start of C3 ELANE XCVR Channel 0 Loopback mode
    
    	INFO: Polling For PMA Register: Read  XCVR CSR Register offset = 0x8a, data = 0x80 
    	INFO: Polling For PMA Register: Read  XCVR CSR Register offset = 0x8b, data = 0x8e 
    
    	INFO: C3 ELANE XCVR Channel 0 Loopback mode is successfully enabled 
    
    	INFO: Channel 0 initial adaptation 
    
    	INFO: Polling For PMA Register: Read  XCVR CSR Register offset = 0x8a, data = 0x80 
    	INFO: Polling For PMA Register: Read  XCVR CSR Register offset = 0x8b, data = 0x8c 
    	INFO: Channel 0 initial adaptation status
    	INFO: Polling For PMA Register: Read  XCVR CSR Register offset = 0x8a, data = 0x80 
    	INFO: Polling For PMA Register: Read  XCVR CSR Register offset = 0x8b, data = 0x8e 
    	INFO: Polling For PMA Register: Read  XCVR CSR Register offset = 0x88, data = 0x80 
    	INFO: Initial adaptation is done successfully on channel 0
    
    INFO: De-assert RX Digital Reset 
    
    INFO: Channel 0: Release RX Reset
    Channel 0 : Wait for measure_valid to assert
    	measure_valid is asserted
    Channel 0 : Get checker_pass status:
    	Checker value = 1
    	Checker status = Passed!
    Channel 0 : Read Determenistic latency counts
    Info: Loop 0 passed
    End of loop 0
    
    
    
    Info: End of c3_cpri_test 
    
    
    Info: Total loop passed = 1/1 
    
    
    Info: Test <c3_cpri_test> Passed 
    
     
    

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