E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

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ID 683860
Date 12/11/2021
Public
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3.1.4. Simulating the Design Example Testbench

Procedure

Follow these steps to simulate the testbench:

  1. At the command prompt, change to the testbench simulation directory <design_example_dir>/example_testbench.
  2. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Refer to the table Steps to Simulate the Testbench.
  3. Analyze the results. The successful testbench received five hyperframes, and displays "PASSED".
    Table 19.  Steps to Simulate the Testbench
    Simulator Instructions
    ModelSim* SE or Questa* In the command line, type vsim -do run_vsim.do

    If you prefer to simulate without bringing up the ModelSim GUI, type vsim -c -do run_vsim.do

    Note: The ModelSim* - Intel® FPGA Edition simulator does not have the capacity to simulate this IP core. You must use another supported ModelSim simulator such as ModelSim* SE.
    VCS* or VCS* MX In the command line, type sh run_vcs.sh or sh run_vcsmx.sh
    Xcelium* In the command line, type sh run_xcelium.sh
    The following sample output illustrates a successful simulation test run for 24.33024 Gbps with 4 CPRI channels:
    waiting for EHIP Ready....
    EHIP READY is 1 at time             424915000
    Enable internal serial loopback...
    ** Address offset = 0x84, WriteData = 0x00000001
    ** Address offset = 0x85, WriteData = 0x00000001
    ** Address offset = 0x86, WriteData = 0x00000008
    ** Address offset = 0x87, WriteData = 0x00000000
    ** Address offset = 0x90, WriteData = 0x00000001
    ** Reading address 0x8a[7] until it changes to 1...
    ** Address offset = 0x8a[7], ReadData  = 0x1
    ** Reading address 0x8b[0] until it changes to 0...
    ** Address offset = 0x8b[0], ReadData  = 0x0
    ** Address offset = 0x8a, WriteData = 0x00000080
    ** Address offset = 0x84, WriteData = 0x00000001
    ** Address offset = 0x85, WriteData = 0x00000001
    ** Address offset = 0x86, WriteData = 0x00000008
    ** Address offset = 0x87, WriteData = 0x00000000
    ** Address offset = 0x90, WriteData = 0x00000001
    ** Reading address 0x8a[7] until it changes to 1...
    ** Address offset = 0x8a[7], ReadData  = 0x1
    ** Reading address 0x8b[0] until it changes to 0...
    ** Address offset = 0x8b[0], ReadData  = 0x0
    ** Address offset = 0x8a, WriteData = 0x00000080
    ** Address offset = 0x84, WriteData = 0x00000001
    ** Address offset = 0x85, WriteData = 0x00000001
    ** Address offset = 0x86, WriteData = 0x00000008
    ** Address offset = 0x87, WriteData = 0x00000000
    ** Address offset = 0x90, WriteData = 0x00000001
    ** Reading address 0x8a[7] until it changes to 1...
    ** Address offset = 0x8a[7], ReadData  = 0x1
    ** Reading address 0x8b[0] until it changes to 0...
    ** Address offset = 0x8b[0], ReadData  = 0x0
    ** Address offset = 0x8a, WriteData = 0x00000080
    ** Address offset = 0x84, WriteData = 0x00000001
    ** Address offset = 0x85, WriteData = 0x00000001
    ** Address offset = 0x86, WriteData = 0x00000008
    ** Address offset = 0x87, WriteData = 0x00000000
    ** Address offset = 0x90, WriteData = 0x00000001
    ** Reading address 0x8a[7] until it changes to 1...
    ** Address offset = 0x8a[7], ReadData  = 0x1
    ** Reading address 0x8b[0] until it changes to 0...
    ** Address offset = 0x8b[0], ReadData  = 0x0
    ** Address offset = 0x8a, WriteData = 0x00000080
    Internal serial loopback is enabled
    Waiting for RX Block Lock
    RX Block Lock is high at time             523408053
    Waiting for RX ready
    RX is ready is high at time             523450000
    *** sending packets in progress, waiting for checker pass ***
    *** waiting for measure_valid to assert...
    ** Address offset = 0xc01[0], ReadData  = 0x1
    ** measure_valid is asserted.
    ** Address offset = 0xc02, ReadData  = 0x0000280a
    ** Address offset = 0xc03, ReadData  = 0x000073c2
    ** Address offset = 0x29, ReadData  = 0x00000026
    *** waiting for hyperframe sync to assert...
    ** hyperframe sync is asserted.
    *** waiting for round trip measure...
    -> 722269000ps: Channel 0: Round trip measure done with count 5058
    ** Channel 0: RX checker has received packets correctly!
    ** PASSED
    *** waiting for measure_valid to assert...
    ** Address offset = 0xc01[0], ReadData  = 0x1
    ** measure_valid is asserted.
    ** Address offset = 0xc02, ReadData  = 0x00002709
    ** Address offset = 0xc03, ReadData  = 0x000072ad
    ** Address offset = 0x29, ReadData  = 0x00000066
    *** waiting for hyperframe sync to assert...
    ** hyperframe sync is asserted.
    *** waiting for round trip measure...
    -> 729769000ps: Channel 1: Round trip measure done with count 4992
    ** Channel 1: RX checker has received packets correctly!
    ** PASSED
    *** waiting for measure_valid to assert...
    ** Address offset = 0xc01[0], ReadData  = 0x1
    ** measure_valid is asserted.
    ** Address offset = 0xc02, ReadData  = 0x000025af
    ** Address offset = 0xc03, ReadData  = 0x000072ad
    ** Address offset = 0x29, ReadData  = 0x00000046
    *** waiting for hyperframe sync to assert...
    ** hyperframe sync is asserted.
    *** waiting for round trip measure...
    -> 736725000ps: Channel 2: Round trip measure done with count 4949
    ** Channel 2: RX checker has received packets correctly!
    ** PASSED
    *** waiting for measure_valid to assert...
    ** Address offset = 0xc01[0], ReadData  = 0x1
    ** measure_valid is asserted.
    ** Address offset = 0xc02, ReadData  = 0x00002836
    ** Address offset = 0xc03, ReadData  = 0x00007590
    ** Address offset = 0x29, ReadData  = 0x00000002
    *** waiting for hyperframe sync to assert...
    ** hyperframe sync is asserted.
    *** waiting for round trip measure...
    -> 786573000ps: Channel 3: Round trip measure done with count 5123
    ** Channel 3: RX checker has received packets correctly!
    ** PASSED
    **
    *****************************************
    $finish called from file "basic_avl_tb_top.sv", line 320.
    $finish at simulation time 786593000ps
    Simulation complete, time is 786593000000 fs.
    

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