E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 12/11/2021
Public

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4.3.2.1. 25GE MAC+PCS with RS-FEC and PTP to CPRI Simulation Dynamic Reconfiguration Design Example Components

The simulation block diagram below is generated using the following settings in the IP parameter editor:
  1. 25G Ethernet to CPRI Protocol as DR Protocol.
  2. Under the 25G Ethernet to CPRI Protocol tab:
    1. 25G PTP RS-FEC as Select DR Design.
    2. Other Development Kits as the target development kit.
Figure 35. Simulation Block Diagram for E-Tile Ethernet IP for Intel® Agilex™ FPGA 25G Ethernet to CPRI Dynamic Reconfiguration Design Example

The successful test displays the dynamic reconfiguration transition flow between various modes. Use preset HEX file provided for each design example or modify provided C code to enable specific transition simulation. For more information on HEX file, refer to Simulating the E-Tile Dynamic Reconfiguration Design Example Testbench.

To test a specific transition, reorder the dynamic reconfiguration transition flow tests in the main.c file and regenerate a new HEX file. Each test describes a transition from the starting rate to the destination rate.

This is the default simulation test sequence based on the provided HEX file.
  1. Toggle sl_tx_rst_n and sl_rx_rst_n reset signals.
  2. Link Initialization. For more information, refer to Performing the Link Initialization.
  3. Dynamic reconfiguration (DR) test from 25G PTP with RS-FEC to 24G CPRI with RS-FEC
  4. DR test from 24G CPRI with RS-FEC to 10G CPRI
  5. DR test from 10G CPRI to 9.8G CPRI
  6. DR test from 9.8G CPRI to 4.9G CPRI
  7. DR test from 4.9G CPRI to 2.4G CPRI
  8. DR test from 2.4G CPRI to 24G CPRI with RS-FEC
  9. DR test from 24G CPRI with RS-FEC to 25G PTP with RS-FEC
  10. DR test from 25G PTP with RS-FEC to 10G CPRI
  11. DR test from 10G CPRI to 25G PTP with RS-FEC
  12. DR test from 25G PTP with RS-FEC to 9.8G CPRI
  13. DR test from 9.8G CPRI to 25G PTP with RS-FEC
  14. DR test from 25G PTP with RS-FEC to 4.9G CPRI
  15. DR test from 4.9G CPRI to 25G PTP with RS-FEC
  16. DR test from 25G PTP with RS-FEC to 2.4G CPRI
  17. DR test from 2.4G CPRI to 25G PTP with RS-FEC
Each of the dynamic reconfiguration tests follows these steps:
  1. Assert sl_tx_rst_n and sl_rx_rst_n reset signals.
  2. Disable SERDES. Use PMA attribute code 0x0001 in the E-tile Transceiver PHY User Guide: PMA Attribute Codes section.
  3. Perform reference clock mux switching. For more information about the details of the changed register values, refer to the c3_reconfig.c file.
    1. Switch the PMA controller clock to the transceiver refclk1 clock.
    2. Change refclk reference clock from the original speed mode clock to the destination speed mode clock.
      Note: For information on speed mode clocks, refer to 25G Ethernet to CPRI Design Example Interface Signals.
    3. Switch the PMA controller clock to the transceiver refclk0 clock.
    Note: Steps 3a and 3c are only applicable for Ethernet dynamic reconfiguration hardware test to avoid potential hardware glitch due to the reference clock switch operation. These steps are available in the hardware test code but skip in the simulation test code.
  4. Trigger PMA analog reset. For more information about register descriptions, refer to the E-tile Transceiver PHY User Guide.
  5. Reconfigure the registers for the Ethernet, RS-FEC, and transceiver blocks. For more information about register descriptions, refer to the E-tile Transceiver PHY User Guide.
  6. Adjust the phase offset of a recovered clock. Use PMA attribute code 0x000E in the E-tile Transceiver PHY User Guide: PMA Attribute Codes section.
  7. Enable SERDES. Use PMA attribute code 0x0001 in the E-tile Transceiver PHY User Guide: PMA Attribute Codes section.
  8. Enable internal serial loopback. Use PMA attribute code 0x0008 in the E-tile Transceiver PHY User Guide: PMA Attribute Codes section.

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