E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

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ID 683860
Date 12/11/2021
Public
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4.3.3.1. 25GE MAC+PCS with RS-FEC and PTP to CPRI Hardware Dynamic Reconfiguration Design Example Components

The 25G Ethernet to CPRI hardware dynamic reconfiguration design example includes the following components:
  • E-tile Ethernet IP for Intel Agilex FPGA core.
  • Client 10G/25G logic that coordinates the programming of the IP core and packet generation.
  • Client XGMII Pattern Generator and Checker that coordinates the programming of the IP core and packet generation.
  • Client 8B/10B Pattern Generator and Checker that coordinates the programming of the IP core and packet generation.
  • Round trip counter to measure the total round trip delay value via the DUT.
  • IO PLL to provide sampling clock, 250 MHz for DUT and the Round trip counter.
  • Time-of-day (ToD) module to provide a continuous flow of current time-of-day information to the IP core.
  • PIO block to store RX and TX PTP timestamp for accuracy calculation and to send PTP 2-step timestamp request.
  • Avalon® -MM address decoder to decode reconfiguration address space for MAC, transceiver, and RS-FEC modules during reconfiguration accesses.
  • Nios® II System that communicates with the Nios® II Software Build Tools (SBT) for Eclipse. You communicate with the client logic and E-tile Ethernet IP for Intel Agilex FPGA through the tool.

When switching from Ethernet to CPRI protocol mode, the CPRI PHY Soft wrapper module reads the TX and RX datapath latency and Round trip counter values and displays them in the dynamic reconfiguration hardware test. For more information about CPRI PHY registers, refer to the E-tile Hard IP User Guide: E-Tile CPRI PHY Intel FPGA IP section.

The following sample outputs illustrate a successful hardware test run for a 25GE, MAC+PCS, RS-FEC, with PTP IP core variation:
CPU is alive!


             Dynamic Reconfiguration Hardware Test

By default, the starting mode is 25G_PTP_RSFEC.
      Please choose one of Dynamic reconfiguration:
    0) 25G_PTP_RSFEC  -> 10G_PTP -> 25G_PTP_RSFEC -> CPRI_24G_RSFEC -> 
       25G_PTP_RSFEC -> CPRI_10G -> 25G_PTP_RSFEC -> CPRI_9p8G -> 
       25G_PTP_RSFEC -> CPRI_4p9G -> 25G_PTP_RSFEC -> CPRI_2p4G -> 25G_PTP_RSFEC
    1) 25G_PTP_RSFEC  -> CPRI_24G_RSFEC
    2) CPRI_24G_RSFEC -> 25G_PTP_RSFEC
    3) 25G_PTP_RSFEC  -> CPRI_10G
    4) CPRI_10G       -> 25G_PTP_RSFEC
    5) 25G_PTP_RSFEC  -> CPRI_9p8G
    6) CPRI_9p8G      -> 25G_PTP_RSFEC
    7) 25G_PTP_RSFEC  -> CPRI_4p9G
    8) CPRI_4p9G      -> 25G_PTP_RSFEC
    9) 25G_PTP_RSFEC  -> CPRI_2p4G
    a) CPRI_2p4G      -> 25G_PTP_RSFEC
    b) CPRI_24G_RSFEC -> CPRI_10G
    c) CPRI_10G       -> CPRI_9p8G
    d) CPRI_9p8G      -> CPRI_4p9G
    e) CPRI_4p9G      -> CPRI_2p4G
    f) CPRI_2p4G      -> CPRI_24G_RSFEC
    g) 25G_PTP_RSFEC  -> 10G_PTP
    h) 10G_PTP        -> 25G_PTP_RSFEC
    i_ 25G_PTP_RSFEC  -> CPRI_24G_RSFEC -> CPRI_10G -> CPRI_9p8G -> 
       CPRI_4p9G -> CPRI_2p4G -> CPRI_24G_RSFEC -> 25G_PTP_RSFEC
    j) Terminate test
       If you terminate the test halfway, you must reload the .sof file before retrigger the hardware test.

Enter a Valid Selection (0,1,3,5,7,9,g,i,j):
0
You entered: 0. Execute five pairs of dynamic reconfiguration.

INFO: Dynamic reconfiguration: 25G_PTP_RSFEC -> 10G_PTP

INFO: End of dynamic reconfiguration: 25G_PTP_RSFEC -> 10G_PTP
INFO: PKT_RX_CNT received = 20

INFO: Dynamic reconfiguration: 25G_PTP_RSFEC -> CPRI_24G_RSFEC

INFO: End of dynamic reconfiguration: 25G_PTP_RSFEC -> CPRI_24G_RSFEC

INFO: tx_delay info: 26fb
INFO: rx_delay info: 7908
INFO: 24G with FEC rx bitslip value info: 4c
INFO: Total Output RT count value (sample sizes: hardware: 128, sim: 32): 5115
Test Pass!

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