E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

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ID 683860
Date 12/11/2021
Public
Document Table of Contents

2.1.1. Directory Structure

The E-tile Ethernet IP for Intel Agilex FPGA design example file directories contain the following generated files for the design examples.

Figure 2.  E-tile Ethernet IP for Intel Agilex FPGA 10GE/25GE with Optional RS-FEC and Optional PTP Design Example Directory Structure<datarate> is either "10" or "25", depending on your IP core variation.
Figure 3.  E-tile Ethernet IP for Intel Agilex FPGA 100GE with Optional RS-FEC Design Example Directory Structure
Table 2.   E-tile Ethernet IP for Intel Agilex FPGA Core Testbench File Descriptions

File Names

Description

Key Testbench and Simulation Files
<design_example_dir>/example_testbench/basic_avl_tb_top.sv Top-level testbench file. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets.
Testbench Scripts
<design_example_dir>/example_testbench/run_vsim.do The Siemens* EDA ModelSim* SE or Questa* script to run the testbench.
<design_example_dir>/example_testbench/run_vcs.sh The Synopsys* VCS* script to run the testbench.
<design_example_dir>/example_testbench/run_vcsmx.sh The Synopsys* VCS* MX script (combined Verilog HDL and System Verilog with VHDL) to run the testbench.
<design_example_dir>/example_testbench/run_xcelium.sh The Xcelium* script to run the testbench.
Table 3.   Intel® Agilex™ IP Core Hardware Design Example File Descriptions

File Names

Description

<design_example_dir>/hardware_test_design/alt_ehipc3_hw.qpf Intel® Quartus® Prime project file.
<design_example_dir>/hardware_test_design/alt_ehipc3_hw.qsf Intel® Quartus® Prime project settings file.
<design_example_dir>/hardware_test_design/alt_ehipc3_hw.sdc Synopsys Design Constraints files. You can copy and modify these files for your own Intel® Agilex™ design.
<design_example_dir>/hardware_test_design/alt_ehipc3_hw.v Top-level Verilog HDL design example file.
<design_example_dir>/hardware_test_design/common/ Hardware design example support files.
hwtest_sl/main_script.tcl (10GE/25GE)

hwtest/main.tcl (100GE)

Main file for accessing System Console.

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