E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 12/11/2021
Public

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4.5. 100G Ethernet Dynamic Reconfiguration Design Example

The 100G Ethernet E-Tile Dynamic Reconfiguration Design Example demonstrates a dynamic reconfiguration solution for Intel® Agilex™ devices using the E-tile Ethernet IP for Intel Agilex FPGA core with the following variants. The 100G Ethernet E-Tile Dynamic Reconfiguration Design Example supports four PMA channels to create either a single 100G Ethernet channel, or four single 10G/25G Ethernet channels.

Table 43.  List of Supported Design Example Variants for 100G Ethernet Dynamic ReconfigurationAll variants support 156.25 MHz refclk and optional RS-FEC. The external AIB clocking, PTP, and asynchronous clock support are not available in the current implementation.
Base Operation Dynamic Reconfiguration Variants
100GE MAC + PCS with RS-FEC 100G MAC + PCS with RS-FEC
100G MAC + PCS
4x25G MAC + PCS with RS-FEC
4x25G MAC + PCS

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