E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 12/11/2021
Public
Document Table of Contents

4.5.2. Testing the 100G Ethernet Dynamic Reconfiguration Hardware Design Example

After you compile the 100G Ethernet E-Tile Dynamic Reconfiguration Design Example and configure it on your device, you can use the procedures to program the IP core.

Table 44.  100G Ethernet Dynamic Reconfiguration Hardware Design Example Functions
Command Setting Description
start_random_pkt_gen_4ch

Starts the packet generator in a random size mode for all four channel lanes.

Example: %start_random_pkt_gen_4ch

stop_pkt_gen_4ch

Immediately stops the packet generator for all four channel lanes.

chkmac_stats $ch

Checks the mac stats counter for the specified channel.

Example:
  • In 100GE mode: %chkmac_stats
  • In 25GE mode: %chkmac_stats 2 for lane 2
run_test_dr

Switches between all available modes and performs the traffic test for each reconfiguration. In 25GE mode, performs four traffic tests, one per each lane.

run_test_dr_sw

Switches to a specified mode and performs the traffic test in a loopback mode.

dr_calib_switch $mode_curr $mode_target

Reconfigures to a different mode based on the configuration and a $mode_target variable. Performs the PMA adaptation for the specific mode.

$mode_target options:
  • 100G_fec
  • 100G_nofec
  • 4x25G_fec
  • 4x25G_nofec
$more_curr variable supports all target modes.
Note: $mode_curr is not a required parameter.
Example:
  • In 100GE mode, use this command to switch to 4x25GE: dr_calib_switch 0 "100g_fec" "4x25G_nofec"
  • In 25GE mode, use this command to switch to 4x25GE: dr_calib_switch 0 "" "4x25G_nofec" as $mode_curr isn't required.
dr_reset Resets all signals except the PMA and E-tile Hard IP for Ethernet CSRs.

Below tables describe dr_reset sequence. You need to assert the 4-bit register in a step pattern: 0x8 > 0xC > 0xE > 0xF > 0xE > 0xC > 0x8 > 0x0. Assume 1 ms delay between each step.

Table 45.  Reset sequence assertionThis table illustrates dr_reset[3:0] assertion sequence.
Assertion Sequence dr_reset[3:0]={Channel3, Channe2, Channe1, Channel0}

Channel 3

Channel 2

Channel 1

Channel 0

(Master Channel)

1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
Table 46.  Reset sequence deassertionThis table illustrates dr_reset[3:0] deassertion sequence.
Assertion Sequence dr_reset[3:0]={Channel3, Channe2, Channe1, Channel0}

Channel 3

Channel 2

Channel 1

Channel 0

(Master Channel)

1 1 1 1 1
2 1 1 1 0
3 1 1 0 0
4 0 0 0 0

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