22.214.171.124. 10GE/25GE Design Example
To turn on the System Console and test the hardware design example, follow these steps:
- After the hardware design example is configured on the Intel® Agilex™ device, in the Intel® Quartus® Prime Pro Edition software, on the Tools menu, click In-System Sources and Probes Editor.
- In the JTAG Chain Configuration window, select the USB connection that is connected to the development kit.
- Next, from the Device list, select the device with 1ST280EY string in the name. The Ready to acquire status appears at the bottom of the Instance Manager window if the correct device is selected.
- A list of instances appears once the connection is acquired. There are four sources under index 0. These sources have the following connections:
Source Signal source sl_csr_rst_n (active low) source sl_tx_rst_n (active low) source sl_rx_rst_n (active low) source i_reconfig_reset (active high)
- Toggle source to initiate reset for the transceiver and Ethernet reconfiguration interfaces.
- Once the reset is initiated, on the Tools menu, click System Debugging Tools > System Console.
- In the Tcl Console pane, type cd hwtest_sl to change directory to <design_example_dir>/hardware_test_design/hwtest_sl.
- Type set <command_setting> to configure the test according to your design configuration:
Command Setting Description totalChannel Set this value according to the value of Number of Channels of 10GE/25GE parameter in your design. The default value is 1.
Example, in the system console type set totalChannel 2 to change the number of channels to 2.Note: E-tile Ethernet IP for Intel Agilex FPGA does not support multichannel PCS variation.
jtag_port_id Set this value to the JTAG port ID that is connected to the development kit.
Example, in the system console type set jtag_port_id 0 to change the JTAG ID to 0.
enableILB Set this to 1 to enable Internal Serial Loopback. The default value is 1.
Example, in the system console, type set enableILB 0 to disable Internal Serial Loopback.
enablePTP Set this to 1 if PTP is enabled in the design. Otherwise set the value to 0. The default value is 0.
Example, in the system console type set enablePTP 1 to enable PTP.
speed Choose the following option according to the design example variation:
- 10G for 10 Gbps data rate
- 25G for 25 Gbps data rate
- 25G_fec for 25 Gbps data rate with RS-FEC enabled
- pcsonly for PCS only and custom PCS designs
- pcsonly_fec for PCS only and custom PCS designs with RS-FEC enabled
Example, in the system console type set speed 25G_fec to set the data rate to 25G with RS-FEC enabled.
PMAadaptation Set this to 1 if Enable adaptation load soft IP parameter is enabled in your design. Otherwise, set the value to 0. The default value is 0. PMAConfig Set the PMA configuration number to enable PMA adaptation. The PMA configuration number set must be one of the PMA configurations defined in your design. EnhancedPTPAccuracy Set this to 1 if Advanced PTP Accuracy Mode is enabled in the design. Otherwise set the value to 0. The default value is 0.
Example, in the system console type set EnhancedPTPAccuracy 1 to enable Advanced PTP Accuracy Mode.
- Type source main_script.tcl to enable the internal loopback and run the test.
% set totalChannel 1 1 % set jtag_port_id 0 0 % set enablePTP 0 0 % set speed 25G 25G % set PMAadaptation 1 1 % set PMAConfig 0 0 % source main_script.tcl Info: Number of Channels = 1 Info: JTAG Port ID = 0 Info: PTP Enable = 0 Info: Speed = 25G Info: PMA Adaptation = 1 Info: PMAConfig Number = 0
Set the speed to pcsonly to configure 10GE/25GE PCS only with optional RS-FEC hardware test. Set the speed to pcsonly_fec to configure 10G/25G custom PCS with optional RS-FEC hardware test.
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