E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

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ID 683860
Date 12/11/2021
Public
Document Table of Contents

3.2.1. Features

  • TX and RX serial loopback mode
  • Generate the design example with RS-FEC feature
  • PMA adaptation
  • Supports TX and RX external loopback mode when you turn on PMA adaptation feature
  • Basic packet checking capabilities including round trip latency count
  • Ability to use System Console to reset the design for re-testing purpose

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