E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

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ID 683860
Date 12/11/2021
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2.3.6. 100GE PCS with Optional RS-FEC Design Example Registers

Table 15.   E-tile Ethernet IP for Intel Agilex FPGA Hardware Design Example Register MapLists the memory mapped register ranges for the hardware design example. You access these registers with the reg_read and reg_write functions in the System Console.
Word Offset Register Type
0x000000 KR4 registers
0x000300 RX PCS registers
0x00F000 Packet Generator and Checker registers
0x010000 RS-FEC configuration registers
0x100000 Transceiver registers
Table 16.  Packet Generator and Checker Registers You can customize the E-tile Ethernet IP for Intel Agilex FPGA hardware design example by programming the packet client registers.

Addr

Name

Bit

Description

HW Reset Value

Access

0xF000 Control Register 0 [0] Write 1 to start transmitting PCS packets. 0x0 RWC
0xF001 Control Register 1 [0] Write 1 to reset the channel. 0x0 RW
0xF002 XGMII Status register [6:0]
  • Bit [0]: value 1 indicates the RX path is ready to receive packet
  • Bit [1]: Value 1 indicates the packets are verified and passed.
  • Bit [2]: Value 1 indicates there is an error with the received packets.
  • Bit [3]: Value 1 indicates the FIFO is full.
  • Bit [4]: Value 1 indicates the test is completed.
  • Bit [5]: Value 1 indicates all frames completed transmission and reception.
  • Bit [6]: value 1 indicates the test has passed.
.
0x0 RO
0xF003 GMII Status register [5:0]
  • Bit [0]: value 1 indicates the GMII RX path is ready to receive packet
  • Bit [1]: Value 1 indicates the auto-negotiation completed.
  • Bit [2]: Value 1 indicates packet generation completed.
  • Bit [3]: Value 1 indicates packet verification completed.
  • Bit [4]: Value 1 indicates is an error with the received packets.
  • Bit [5]: value 1 indicates the test has passed.
0x0 RO
0xF006 max_frame register [31:0] Specify the maximum number of frames for transmission. 0x0 RW
0xF007 frame_length register [31:0] Specify the packet size. 0x0 RW
0xF008 XGMII_data_match_count [255:0] Report the number of XGMII passed packets. 0x0 RO
0xF009 XGMII_data_mismatch_count [255:0] Reports the number of XGMII error packets. 0x0 RO
0xF00A frame_type [2:0]
  • 001: Fixed mode
  • 010: Incremental mode
  • 100: Random mode
0x0 RW
0xF00B PXGMII_client_loopback [0] Set the value to 1 to enable XGMII RX loopback to XGMII TX. 0x0 RW

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