E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 12/13/2021

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2.12. Register Descriptions

You access the Ethernet registers for the E-Tile Hard IP for Ethernet Intel FPGA IP using the Avalon® memory-mapped Ethernet reconfiguration interface on each channel. The TX and RX RS-FEC registers are accessible through the RS-FEC reconfiguration interface.

Write operations to a read-only register field have no effect. Read operations that address a Reserved register return an unspecified result. Write operations to Reserved registers have no effect. Accesses to registers that do not exist in your IP core variation, or to register bits that are not defined in your IP core variation, have an unspecified result. You should consider these registers and register bits Reserved. Although you can only access registers in 32-bit read and write operations, you should not attempt to write or ascribe meaning to values in undefined register bits.

Table 71.  Register Base AddressesThe reset values in register type sections represent register values after a reset has completed. These registers use 32-bit addresses; they are not byte accessible.
Word Offset Register Type
0x0B0-0x0E8 Auto Negotiation and Link Training registers
0x300-0x3FF PHY registers
0x400-0x4FF TX MAC registers
0x500-0x5FF RX MAC registers
0x600-0x7FF Pause and Priority- Based Flow Control registers
0x800-0x8FF TX Statistics Counter registers
0x900-0x9FF RX Statistics Counter registers
0xA00-0xAFF TX 1588 PTP registers
0xB00-0xBFF RX 1588 PTP registers
Table 72.  RS-FEC Register Base Addresses
Word Offset Register Type
0x000-0x2FF TX and RX RS-FEC registers
Table 73.  Transceiver Register Base AddressesPTP transceiver channel register is accessed through the PTP reconfiguration interface. Data transceiver channel register is accessed through the Transceiver reconfiguration interface.
Word Offset Register Type
0x40000-0x40144 PMA Capability registers
0x000-0x207 PMA AVMM registers
Note: Do not attempt to access any register address that is Reserved or undefined. Accesses to registers that do not exist in your IP core variation have unspecified results.

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