|Data Rate per Channel||Number of Channels||Core Interface|
|25.78125 Gbps||4||64 bits|
Master-Slave Configuration: Option 1
All four channels use a common FEC block but FEC will use only one clock from the 4 available channels. The channel that provides the FEC clock is considered as a master. The other 3 channels use that same clock for clocking their TX and RX data path, and are considered as slave channels. Any interruption on master channel PMA, a PMA reset, for example, impacts the slave channels. This creates a dependency between the master and the slave channels.
Connect o_clk_pll_div64 (402.83MHz) to the i_sl_clk_tx and i_sl_clk_rx. If you use any other source for i_sl_clk_tx or i_sl_clk_rx, make sure i_sl_clk_tx and i_sl_clk_rx have 0 PPM difference with the o_clk_pll_div64.
Master-Slave Configuration: Option 2 - External AIB Clocking Scheme
- Wait until o_tx_pll_locked output from the PLL channel is asserted before deasserting the transceiver channel reset at power-up.
- If o_tx_pll_locked from the PLL channel is deasserted at any time, hold the respective transceiver channel in reset until o_tx_pll_locked is reasserted.
The following figure shows one master 25 Gbps channel providing the datapath clock to other three slave 25 Gbps channels. This method removes the dependency of a PMA reset between the Master and Slave channels.
Master-Slave Configuration: Option 3 - Dynamic Reconfiguration
In this configuration, you can dynamically reconfigure the Master Channel 0 from 25G to 10G. This configuration uses four 25G Ethernet channels with RS-FEC enabled at power on. Channel 0 is considered the Master channel and channel 1 ~ channel 3 are considered Slave channels. After power on, the 25G Master Channel with RS-FEC enable reconfigures from 25.78125 Gbps to 10.3125 Gbps.
Below figure is an example of possible dynamic reconfiguration on Master channel. You can reconfigure the master channel to any mode without bringing down the slave channel functionality with the exception of the direct PMA.
For more information on the dynamic reconfiguration examples, refer to the Dynamic Reconfiguration Design Example User Guide.
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