3.7.3. Generated File Structure
For information about the file structure of the design example, refer to the device specific E-tile Hard IP Intel Stratix 10 Design Examples User Guides or E-tile Hard IP Intel® Agilex™ FPGA IP Design Examples User Guides.
The Platform Designer system or top-level IP variation file. <your_ip> is the name that you give your IP variation.
|<your_ip>.cmp||The VHDL Component Declaration (.cmp) file is a text file that contains local generic and port definitions that you can use in VHDL design files.|
A report that contains connection information, a memory map showing the address of each slave with respect to each master to which it is connected, and parameter assignments.
|<your_ip>_generation.rpt||IP or Platform Designer generation log file. A summary of the messages during IP generation.|
|<your_ip>.qgsimc||Lists simulation parameters to support incremental regeneration.|
|<your_ip>.qgsynthc||Lists synthesis parameters to support incremental regeneration.|
Contains all the required information about the IP component to integrate and compile the IP component in the Intel® Quartus® Prime software.
Describes the connections and IP component parameterizations in your Platform Designer system. You can parse its contents to get requirements when you develop software drivers for IP components.
Downstream tools such as the Nios® II tool chain use this file. The .sopcinfo file and the system.h file generated for the Nios® II tool chain include address map information for each slave relative to each master that accesses the slave. Different masters may have a different address map to access a particular slave component.
|<your_ip>.csv||Contains information about the upgrade status of the IP component.|
Required input file for ip-make-simscript to generate simulation scripts for supported simulators. The .spd file contains a list of files generated for simulation, along with information about memories that you can initialize.
|<your_ip>_bb.v||You can use the Verilog black-box (_bb.v) file as an empty module declaration for use as a black box.|
|<your_ip>_inst.v or _inst.vhd||HDL example instantiation template. You can copy and paste the contents of this file into your HDL file to instantiate the IP variation.|
Allows hard processor system (HPS) System Debug tools to view the register maps of peripherals connected to HPS in a Platform Designer system.
During synthesis, the .svd files for slave interfaces visible to System Console masters are stored in the .sof file in the debug section. System Console reads this section, which Platform Designer can query for register map information. For system slaves, Platform Designer can access the registers by name.
|<your_ip>.v or <your_ip>.vhd||HDL files that instantiate each submodule or child IP core for synthesis or simulation.|
Contains a Siemens* EDA ModelSim* SE or Questa* script msim_setup.tcl to set up and run a simulation.
Contains a shell script vcs_setup.sh to set up and run a Synopsys* VCS* simulation.
Contains a shell script vcsmx_setup.sh and synopsys_ sim.setup file to set up and run a Synopsys* VCS* MX simulation.
|submodules/||Contains HDL files for the IP core submodules.|
|<child IP cores>/||For each generated child IP core directory, Platform Designer generates synth/ andsim/ sub-directories.|
Did you find the information on this page useful?