E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 12/13/2021
Public

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Document Table of Contents

3.12. Document Revision History for the E-tile CPRI PHY Intel FPGA IP

Document Version Intel® Quartus® Prime Version IP Version Changes
2021.12.13 21.4 19.6.0
  • Removed support for the NCSim simulator.
  • Added support for the Questa* simulator.
2021.03.29 21.1 19.4.2 Modified the values in Table: Deterministic Latency Measurement for Each Variant.
2020.06.29 20.2 19.4.1
  • Modified the value of UI constant in TX delay deterministic latency calculation formula for 2.4376/3.0720 Gbps CPRI line rates in Table: Deterministic Latency Measurement for Each Variant.
  • Added new register dl_master_reset in Table: CPRI PHY Registers.
2020.04.28 20.1 19.4.1
  • Added resource utilization numbers for Intel® Agilex™ devices in section Resource Utilization.
  • RX clock domain changed to use the RX recovered clock.
  • Updated Figure: E-tile CPRI PHY (FEC On) Master-Slave Configuration to include RX clock domain change.
  • Updated information in Table: Reset Signal and Register Functions .
  • Updated signal domain information from o_tx_clkout2[n] to o_rx_clkout2[n]in the following tables:
    • Table: CPRI PHY RX MII Interface
    • Table: CPRI PHY RX 8B/10B Interface
    • Table: CPRI PHY Status Interface Signals for 8B/10B Interface
  • Corrected address range for the CPRI PHY registers in Table: E-Tile CPRI PHY IP Core AVMM Address Ranges.
  • Updated [3:0] bit description of the 0xC00 register for 3.0, 6.1, and 10.1 Gbps data rates in Table: CPRI PHY Registers.
2020.03.30 19.4 19.4.0 Modified the description of latency factors RxBitSlipH and RxBitSlipL in Table: Latency Calculation Description.
2020.03.09 19.4 19.4.0
  • Corrected TX Delay and RX Delay values in Table: Deterministic Latency Measurement for Each Variant
  • Added factors RxBitSlipH and RxBitSlipL in Latency Calculation Description
2019.12.16 19.4 19.4.0
  • Added support for the Intel® Agilex™ device with E-tile transceivers.
  • The E-Tile CPRI PHY IP now supports the following new CPRI line rates: 3.0720, 6.1440, 10.1316 (with RS-FEC), 12.1651 (with and without RS-FEC).
  • Updated resource utilization numbers in Table: Resource Utilization for Selected Variations.
  • Added Figure: E-Tile CPRI PHY (FEC On) Master-Slave Configuration in section E-Tile CPRI PHY Intel FPGA IP Channel Placement.
  • Updated the following sections to include RS-FEC clocking mode information:
    • One 24.33024 Gbps channel with RS-FEC
    • Two 24.33024 Gbps Channel with RS-FEC
    • Three 24.33024 Gbps Channel with RS-FEC
    • Four 24.33024 Gbps Channel with RS-FEC
  • Updated Restrictions section to include new CPRI line rates information.
  • Added new parameter RSFEC Clocking Mode in Table: Parameter Settings: IP Tab.
  • Updated PHY Reference Clock Frequency for new supported CPRI line rates in Table: Parameter Settings: IP Tab.
  • Updated description for the UI_constant_offset_[rx,tx] in Table: Latency Calculation Description.
  • Updated Table: Reset Signal and Register Functions in section Soft Reset Sequencer.
2019.10.22 19.2 19.2.0 Corrected the frequency value of i_clk_ref for CPRI line rates 2.4/4.9/9.8 Gbps in Table: CPRI PHY Clock Input Signals.
2019.08.07 19.2 19.2.0
  • The E-Tile CPRI PHY IP now supports CPRI line rates: 2.4376, 4.9152, 9.8304, and 24.33024 Gbps (without RS-FEC).
  • Updated Figure: E-tile CPRI PHY Block Diagram.
  • Added new parameters First RSFEC Lane and Enable reconfiguration to 8b/10b datapath in Table: Parameter Settings: IP Tab.
  • Updated the NPDME parameter description in section Parameter Settings.
  • Added the following new sections:
    • TX 8B/10B Interface
    • RX 8B/10B Interface
    • Status Interface for 8B/10B Line Rate
  • Clarified that RX signals are resynchronized to the TX domain.
  • Added deterministic latency calculation equation for the new supported CPRI line rates in section Deterministic Latency Calculation.
  • Updated section E-Tile CPRI PHY Intel FPGA IP Channel Placement.
  • Updated section CPRI PHY Functional Blocks.
  • Modified port names in the following sections:
    • CPRI PHY Reconfiguration Interface
    • Transceiver Reconfiguration Interface
    • RS-FEC Reconfiguration Interface
  • Added calibration requirement in section Minimizing PMA Adaptation Time.
2019.05.17 19.1 19.1 Initial release.

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