E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 12/13/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents TX Pause Request

Offset: 0x606

TX Pause Request Fields

Bit Name Description Access Reset
8:0 req_pause Request TX PAUSE or TX PFC.

Bits [7:0]: For PFC

Bit [8]: For PAUSE

Set to request the transmission of TX Pause frames

Works the same way as the corresponding tx_pause port or tx_pfc port

RW 0x0