E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 12/13/2021
Public

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2.9.1.2.2. RX Strict SFD Checking

The E-Tile Hard IP for Ethernet Intel FPGA IP RX MAC checks all incoming packets for a correct Start byte (0xFB).

If you turn on Enable strict preamble check in the E-Tile Hard IP for Ethernet Intel FPGA IP parameter editor, the RX MAC requires all RX packets to have an Ethernet standard preamble (0x55_55_55_55_55_55). If you turn on Enable strict SFD check , the RX MAC requires all RX packets to have an Ethernet standard Start Frame Delimiter (0xD5).

Strict checking reduces the incidence of runt packets caused by bit errors on the line. However, do not use strict checking in applications where custom preamble values or SFD values are needed.

Table 20.  Strict SFD Checking Configuration
Enable Strict SFD Check 0x50A[4]: Preamble Check 0x50A[3]: SFD Check Fields Checked Behavior if Check Fails
Off Don't Care Don't Care Start byte IP core does not recognize a malformed Start byte as a Start byte
On 0 0 Start byte
0 1 Start byte and SFD IP Core drops the packet
1 0 Start byte and preamble
1 1 Start byte and preamble and SFD

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