E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 12/13/2021

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Document Table of Contents 100G Ethernet with PTP

Connect o_clk_pll_div64[4] (402.83MHz) to the i_clk_tx and i_clk_rx of each Ethernet channel based on the following guidelines:
Table 70.  Clock Connection Guidelines for 100GbE with enabled PTP and Basic PTP Accuracy Mode
Clock Port PTP Clock Clock Connection Guideline




Connect o_clk_pll_div64[4] to i_clk_tx and i_clk_rx.