E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 12/13/2021

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Document Table of Contents Set Uniform Holdoff

Offset: 0x60C

Set Uniform Holdoff Fields

Bit Name Description Access Reset
15:0 holdoff_all_quanta Uniform holdoff time
16b minimum holdoff time required of all PFC queues whenen_holdoff_all = 1.
  • Times are programmed in holdoff quanta
    • For 10G and 25G links, 1 Holdoff Quanta = 8 clock cycles
  • Minimum value is 1, but to minimize wasted bandwidth, holdoff should be set as large as possible without exceeding the recommended max value
  • Maximum value for correct operation where holdoff retransmits PFC requests before the previously transmitted Quanta expires is:
    • For 10G and 25G links: min (Pause Quanta register value) - (60 + Maximum TX Frame Size register value/8)
      • For example, if the minimum pfc pause quanta over all queues is 500, and the max tx frame size is 800 bytes, the max holdoff quanta is 500-(60+100) = 340
      • These values are based on the maximum overrun limits defined in IEEE 802.3 2015 Annex 31B
    • For 100Gx4 links: min(Pause Quanta register value) - (50 + Maximum TX Frame Size register value/32)
  • At power up this register defaults to 0
  • After i_csr_rst_n is asserted, this register value is set according to the module parameter uniform_holdoff_quanta
RW 0x0

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