E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 12/13/2021
Public

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3.10.4. TX 8B/10B Interface

The TX 8b/10b interface is available only when you select the Enable reconfiguration to 8b/10b datapath parameter or when you select the 8b/10b CPRI line rate. For the CPRI PHY core power up in 64b/66b line rate, the IP core asserts these signals when you reconfigure the core at runtime to enter 8b/10b line rate.

Table 98.  CPRI PHY TX 8B/10B Interface
Port Name Width Domain Description
i_sl_tx_d[n] 16 bits per channel o_tx_clkout2[n] Indicates 8b/10b TX data for the corresponding CPRI PHY channel.
i_sl_tx_c[n] 2 bits per channel o_tx_clkout2[n] Indicates 8b/10b TX control for the corresponding CPRI PHY channel.
When you transmit the data using the TX 8b/10b interface:
  • The frames are 8b/10b encoded.
    • Each byte in i_sl_tx_d has a corresponding bit in i_sl_tx_c that indicates whether the byte is a control byte or a data byte. For example, i_sl_tx_c[1] is the control bit for i_sl_tx_d[15:8].
  • The byte order for the TX interface flows from right to left and the first byte that the core transmits is i_sl_tx_d[7:0].
  • The first bit that the core transmits is i_sl_tx_d[0].

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