E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 12/13/2021
Public

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3.10.9.2. Transceiver Reconfiguration Interface

Table 104.  Transceiver Reconfiguration Signals
Port Name Width Domain Description
i_xcvr_reconfig_address[n] 19 bits per channel i_reconfig_clk Specifies transceiver Avalon® memory-mapped interface address in a selected channel.
i_xcvr_reconfig_read[n] 1 bit per channel i_reconfig_clk The IP core asserts this transceiver read signal to start a read cycle in a selected channel.
i_xcvr_reconfig_write[n] 1 bit per channel i_reconfig_clk The IP core asserts this transceiver write signal to write data on reconfig_writedata bus in a selected channel.
i_xcvr_reconfig_writedata[n] 8 bits per channel i_reconfig_clk Specifies transceiver data to be written on a write cycle in a selected channel.
o_xcvr_reconfig_readdata[n] 8 bits per channel i_reconfig_clk Specifies transceiver data to be read by a ready cycle in a selected channel.
o_xcvr_reconfig_waitrequest[n] 1 bit per channel i_reconfig_clk Represents transceiver Avalon® memory-mapped interface stalling signal in selected channel. The read and write cycle is only complete when this signal is low.

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