E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 12/13/2021
Public

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2.9.2.15. Logic Lock Regions Requirements for PTP Accuracy Advanced Mode

The PTP Accuracy advanced mode requires you to add the logic lock region assignment statement in the .qsf file. To add the logic lock assignments, copy the alt_ehipc3_10g25g_ptp_advancedmode_logiclockreg_gen.tcl script, located in the <Generated HDL directory>/alt_ehipc3_2021/synth/" directory into the same location as the .qsf project file.
Follow these steps to add logic lock regions to your .qsf file:
  1. In Intel® Quartus® Prime Pro Edition software, run the initial compilation to place channels in the required location.
  2. In the command line, execute the alt_ehipc3_10g25g_ptp_advancedmode_logiclockreg_gen.tcl script with the following command:
    quartus_sta -t alt_ehipc3_10g25g_ptp_advancedmode_logiclockreg_gen.tcl -project <project name> [-revision <revision name>] [-file <output file name>]
    Note: The project name is a required field. The revision name is an optional field.
  3. Re-run the compilation step to compile the design with added logic lock regions .qsf assignments.

Whenever you perform additional design change or design optimization, you only need to execute step 3. If you change the channel placement or select a different E-tile, you must delete previously generated logic lock regions and execute steps 1 through 3 to regenerate the logic lock regions with the new channel location.

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