E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 12/13/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.9.1.3. Latency Measurement

The latency measurement in the E-Tile CPRI PHY Intel FPGA IP measures the delay between the FPGA core and the serial pins.

Did you find the information on this page useful?

Characters remaining:

Feedback Message