E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 12/13/2021
Public

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2.9.1.2.4. RX Malformed Packet Handling

While receiving an incoming packet from the Ethernet link, the RX MAC expects packets to end with a Terminate Control byte. Packets that contain Error bytes or a control byte other than Terminate are malformed packets. The RX MAC asserts o_rx_error[0] when the frame ends to indicate that it was a malformed packet.

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