E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 12/13/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.10.5. RX 8B/10B Interface

The RX 8b/10b interface is available only when you select the Enable reconfiguration to 8b/10b datapath parameter or you select the 8b/10b CPRI line rate. For the CPRI PHY core power up in 64b/66b line rate, the IP core asserts these signals when you reconfigure the core at runtime to enter 8b/10b line rate.

Table 99.  CPRI PHY RX 8B/10B Interface
Port Name Width Domain Description
i_sl_rx_d[n] 16 bits per channel o_rx_clkout2[n] Indicates 8b/10b RX data for the corresponding CPRI PHY channel.

i_sl_rx_c[n] 2 bits per channel o_rx_clkout2[n] Indicates 8b/10b RX control for the corresponding CPRI PHY channel.

When you transmit the data using the RX 8b/10b interface:
  • The frames are 8b/10b encoded.
    • Each byte in i_sl_rx_d has a corresponding bit in i_sl_rx_c that indicates whether the byte is a control byte or a data byte. For example, i_sl_rx_c[0] is the control bit for i_sl_rx_d[7:0].
  • The byte order for the RX interface flows from right to left and the first byte that the core receives is i_sl_rx_d[7:0].
  • The first bit that the core receives is i_sl_rx_d[0].

Did you find the information on this page useful?

Characters remaining:

Feedback Message