E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 12/13/2021
Public

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Document Table of Contents

2.12.1.17. Consortium Next Page Link Partner Status

Offset: 0xCE

Consortium Next Page Link Partner Status Fields

Bit Name Description Access Reset
27:24 lp_consortium_next_page_fec Link Partner Consortium Next Page FEC Ability

Contain bits D27:D24 from the decoded consortium Unformatted Next Page with the following bits defined by the consortium:

[24]: F1- CL91 RS-FEC ability

[25]: F2- CL74 RS-FEC ability

[26]: F3- CL91 RS-FEC request

[27]: F4- CL74 RS-FEC request

RO 0x0
19:0 lp_consortium_next_page_tech Link Partner Consortium Next Page Technology Ability

[8:0]: Contain bits D8:D0 from the decoded consortium Unformatted Next Page (default of 0x003) to indicate extended technology abilities.

[19:9]: Contain bits D26:D16 from the decoded consortium Unformatted Next Page with the following bits defined by the consortium:

  • [12:9]: Reserved

  • [13]: 25GBASE-KR1 ability

  • [14]: 25GBASE-CR1 ability

  • [16:15]: Reserved

  • [17]: 50GBASE-KR2 ability

  • [18]: 50GBASE-CR2 ability

  • [19]: Reserved

RO 0x0

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