E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 12/13/2021
Public

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Document Table of Contents

2.12.3.6. TX MAC Configuration

Offset: 0x40A

TX MAC Configuration Fields

Bit Name Description Access Reset
3 en_saddr_insert Enable Source Address Insertion

0: Client provides Source Address

1: TX MAC inserts source addresses stored in CSRs
  • At power-up, en_saddr_insert is set to 0
  • After i_csr_rst_n, en_saddr_insert is set to the value given by source_address_insertion
RW 0x0
2 disable_txmac Disable TX MAC

0: TX MAC operates normally

1: TX MAX is disabled - it behaves as though it has been PAUSED by the remote link until disable is turned off

RW 0x0
1 disable_txvlan Disable VLAN detection for TX Stats

0: TX frames with VLAN headers will be counted as VLAN frames in the TX stats

1: VLAN headers will not be considered by the TX stats block
  • At power-on, disable_txvlan is set to 1
  • After i_csr_rst_n is asserted, disable_vlan is set to the value given by module parameter tx_vlan_detection
RW 0x0

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