E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 12/13/2021
Public

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2.12.2.48. Timer Window for Hi-BER Checks

Offset: 0x37A

Timer Window for Hi-BER Checks Fields

Bit Name Description Access Reset
20:0 cycles Timer window for BER measurements

Sets the timer window for BER measurements in clock cycles.

The Ethernet Standard (IEEE 802.3) defines the required times for Hi-BER measurements for each rate. These times must be converted to clock cycles with accurate within +1% and -25% of the specified times.
Note: The clock rate you are using is different from the clock rate used to calculate the cycle count, you will need to scale the cycle count.
  • 100GBASE-R4: 21'd201415 (from Clause 82, 0.5ms +1%,-25% at 402.3 MHz
  • 100GBASE-R2/4: 21'd207518 (from Clause 82, 0.5ms +1%,-25% at 415.039 MHz
  • 25GBASE-R1: 21'd806451 (from Clause 107, 2.0 ms +1%, -25% at 402.3 MHz
  • 10GBASE-R1: 21'd20141 (from Clause 49, 0.125ms +1%, -25% at 161.13 MHz
  • 10GBASE-R1: 21'd50403 (from Clause 49, 0.125ms +1%, -25% at 402.83 MHz

The RX PCS must be reset after changing this value.

RW 0x312C7

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