E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 12/13/2021
Public

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Document Table of Contents

2.12.7.1. RX Statistics Registers

Table 75.  Receive Side Statistics Registers

Address

Name

Description

Access

0x900

RX_FRAGMENTS_31_0

Number of received frames less than 64 bytes and reporting a CRC error (lower 32 bits)

RO

0x901

RX_FRAGMENTS_63_32

Number of received frames less than 64 bytes and reporting a CRC error (upper 32 bits)

RO

0x902

RX_JABBERS_31_0

Number of received oversized frames reporting a CRC error (lower 32 bits)

RO

0x903

RX_JABBERS_63_32

Number of received oversized frames reporting a CRC error (upper 32 bits)

RO

0x904

RX_FCSERR_31_0

Number of received packets with FCS errors. This register maintains a count of the number of pulses on the l<n>_rx_fcs_error or rx_fcs_error output signal (lower 32 bits)

RO

0x905

RX_FCSERR_63_32

Number of received packets with FCS errors. This register maintains a count of the number of pulses on the l<n>_rx_fcs_error output signal (upper 32 bits)

RO

0x906

RX_CRCERR_OKPKT_31_0

Number of received frames with a frame of length at least 64, with CRC error (lower 32 bits)

RO

0x907

RX_CRCERR_OKPKT_63_32

Number of received frames with a frame of length at least 64, with CRC error (upper 32 bits)

RO

0x908

RX_MCAST_DATA_ERR_31_0

Number of errored multicast frames received, excluding control frames (lower 32 bits)

RO

0x909

RX_MCAST_DATA_ERR_63_32

Number of errored multicast frames received, excluding control frames (upper 32 bits)

RO

0x90A

RX_BCAST_DATA_ERR_31_0

Number of errored broadcast frames received, excluding control frames (lower 32 bits)

RO

0x90B

RX_BCAST_DATA_ERR_63_32

Number of errored broadcast frames received, excluding control frames (upper 32 bits)

RO

0x90C

RX_UCAST_DATA_ERR_31_0

Number of errored unicast frames received, excluding control frames (lower 32 bits)

RO

0x90D

RX_UCAST_DATA_ERR_63_32

Number of errored unicast frames received, excluding control frames (upper 32 bits)

RO

0x90E

RX_MCAST_CTRL_ERR_31_0

Number of errored multicast control frames received (lower 32 bits)

RO

0x90F

RX_MCAST_CTRL_ERR_63_32

Number of errored multicast control frames received (upper 32 bits)

RO

0x910

RX_BCAST_CTRL_ERR_31_0

Number of errored broadcast control frames received (lower 32 bits)

RO

0x911

RX_BCAST_CTRL_ERR_63_32

Number of errored broadcast control frames received (upper 32 bits)

RO

0x912

RX_UCAST_CTRL_ERR_31_0

Number of errored unicast control frames received (lower 32 bits)

RO

0x913

RX_UCAST_CTRL_ERR_63_32

Number of errored unicast control frames received (upper 32 bits)

RO

0x914

RX_PAUSE_ERR_31_0

Number of errored pause frames received (lower 32 bits)

RO

0x915

RX_PAUSE_ERR_63_32

Number of errored pause frames received (upper 32 bits)

RO

0x916

RX_64B_31_0

Number of 64-byte received frames (lower 32 bits), including the CRC field but excluding the preamble and SFD bytes

RO

0x917

RX_64B_63_32

Number of 64-byte received frames (upper 32 bits), including the CRC field but excluding the preamble and SFD bytes

RO

0x918

RX_65to127B_31_0

Number of received frames between 65–127 bytes (lower 32 bits)

RO

0x919

RX_65to127B_63_32

Number of received frames between 65–127 bytes (upper 32 bits)

RO

0x91A

RX_128to255B_31_0

Number of received frames between 128 –255 bytes (lower 32 bits)

RO

0x91B

RX_128to255B_63_32

Number of received frames between 128 –255 bytes (upper 32 bits)

RO

0x91C

RX_256to511B_31_0

Number of received frames between 256 –511 bytes (lower 32 bits)

RO

0x91D

RX_256to511B_63_32

Number of received frames between 256 –511 bytes (upper 32 bits)

RO

0x91E

RX_512to1023B_31_0

Number of received frames between 512–1023 bytes (lower 32 bits)

RO

0x91F

RX_512to1023B_63_32

Number of received frames between 512 –1023 bytes (upper 32 bits)

RO

0x920

RX_1024to1518B_31_0

Number of received frames between 1024–1518 bytes (lower 32 bits)

RO

0x921

RX_1024to1518B_63_32

Number of received frames between 1024–1518 bytes (upper 32 bits)

RO

0x922

RX_1519toMAXB_31_0

Number of received frames between 1519 bytes and the maximum size defined in the MAX_RX_SIZE_CONFIG register (lower 32 bits)

RO

0x923

RX_1519toMAXB_63_32

Number of received frames between 1519 bytes and the maximum size defined in the RXMAC_SIZE_CONFIG register (upper 32 bits)

RO

0x924

RX_OVERSIZE_31_0

Number of oversized frames (frames with more bytes than the number specified in the RXMAC_SIZE_CONFIG register) received (lower 32 bits)

RO

0x925

RX_OVERSIZE_63_32

Number of oversized frames (frames with more bytes than the number specified in the RXMAC_SIZE_CONFIG register) received (upper 32 bits)

RO

0x926

RX_MCAST_DATA_OK_31_0

Number of valid multicast frames received, excluding control frames (lower 32 bits)

RO

0x927

RX_MCAST_DATA_OK_63_32

Number of valid multicast frames received, excluding control frames (upper 32 bits)

RO

0x928

RX_BCAST_DATA_OK_31_0

Number of valid broadcast frames received, excluding control frames (lower 32 bits)

RO

0x929

RX_BCAST_DATA_OK_63_32

Number of valid broadcast frames received, excluding control frames (upper 32 bits)

RO

0x92A

RX_UCAST_DATA_OK_31_0

Number of valid unicast frames received, excluding control frames (lower 32 bits)

RO

0x92B

RX_UCAST_DATA_OK_63_32

Number of valid unicast frames received, excluding control frames (upper 32 bits)

RO

0x92C

RX_MCAST_CTRL_OK_31_0

Number of valid multicast frames received, excluding data frames (lower 32 bits)

RO

0x92D

RX_MCAST_CTRL_OK_63_32

Number of valid multicast frames received, excluding data frames (upper 32 bits)

RO

0x92E

RX_BCAST_CTRL_OK_31_0

Number of valid broadcast frames received, excluding data frames (lower 32 bits)

RO

0x92F

RX_BCAST_CTRL_OK_63_32

Number of valid broadcast frames received, excluding data frames (upper 32 bits)

RO

0x930

RX_UCAST_CTRL_OK_31_0

Number of valid unicast frames received, excluding data frames (lower 32 bits)

RO

0x931

RX_UCAST_CTRL_OK_63_32

Number of valid unicast frames received, excluding data frames (upper 32 bits)

RO

0x932

RX_PAUSE_31_0

Number of received pause frames, with or without error (lower 32 bits)

RO

0x933

RX_PAUSE_63_32

Number of received pause frames, with or without error (upper 32 bits)

RO

0x934

RX_RNT_31_0

Number of received runt packets (lower 32 bits)

A run is a packet of size less than 64 bytes but greater than eight bytes. If a packet is eight bytes or smaller, it is considered a decoding error and not a runt frame, and the IP core does not flag it nor count it as a runt.

RO

0x935

RX_RNT_63_32

Number of received runt packets (upper 32 bits)

A run is a packet of size less than 64 bytes but greater than eight bytes. If a packet is eight bytes or smaller, it is considered a decoding error and not a runt frame, and the IP core does not flag it nor count it as a runt.

RO

0x936

RX_st_31_0

Number of RX frame starts (lower 32 bits) RO
0x937 RX_st_63_32 Number of RX frame starts (upper 32 bits) RO
0x938 RX_lenerr_31_0 Number of RX length errors (lower 32 bits) RO
0x939 RX_lenerr_63_32 Number of RX length errors (upper 32 bits) RO
0x93A RX_pfc_err_31_0 Number of RX PFC frame with CRC error (lower 32 bits) RO
0x93B RX_pfc_err_63_32 Number of RX PFC frame with CRC error (upper 32 bits) RO
0x93C RX_pfc_31_0 Number of RX PFC frames without error (lower 32 bits) RO
0x93D RX_pfc_63_32 Number of RX PFC frames without error (upper 32 bits) RO
0x93E to 0x93F Reserved
0x940 rxstat_revid Returns a 4 byte value indicating the revision of this design RO
0x941 rxstat_scratch 32 bits of scratch register space for testing RW
0x942 to 0x944 Reserved
0x945

RX_CNTR_CONFIG

Bits[2:0]: Configuration of RX statistics counters:
  • Bit[2] = 1: Freeze stats CSRs so that all RX Stats values read from the registers will be from the same moment.
    • Note that the actual stats collection counters are not frozen, but because they are all 'read' at the time of the freeze, they are cleared.
    • If a shadow request is started while snapshot is active, a new capture will be executed.
    • Likewise, if a shadow request is active while snapshot is asserted, a new capture will be executed.
    • While either a shadow request or a capture is active, rx_shadow_on will be high.
    • Snapshot and shadow requests apply to several of the RX PCS counters as well as MAC statistics
  • Bit[1] = 1:Reset the parity error bit in RX Statistics Counter Status
    • Parity error bit will remain in reset until rst_rx_parity is set back to 0
  • Bit[0] = 1: Reset all RX Stats counters
    • RX stats will stay in reset until reset is set back to 0
    • Reset also applies when snapshot or shadow is active, and will clear the AVMM visible registers
    • rst_rx_stats does not clear the parity error bit
Bits[31:3] are Reserved.
RW
0x946 RX_CNTR_STATUS
  • Bit[1] = 1: The CSRs for the RX Statistics are currently frozen, and holding the Stats values from the last time a shadow request was made.
  • Bit[0] = 1: A parity error was detected on at least one of the statistics counters since the last time this bit was cleared.
Bits [31:2] are Reserved.
RO
0x947–0x95F

Reserved

 
0x960 RX_Payload_OctetsOK_31_0 Number of received payload bytes in frames with no FCS, undersized, oversized, or payload length errors. When RX VLAN/SVLAN detection is enabled, VLAN/SVLAN header bytes are also removed from the count. Use snapshot or shadow to freeze the count before reading it to avoid value change while reading the register. RO
0x961 RX_Payload_OctetsOK_63_32 RO
0x962 RX_Frame_OctetsOK_31_0 Number of received bytes in frames with no FCS, undersized, oversized, or payload length errors. Use snapshot or shadow to freeze the count before reading it to avoid value change while reading the register. RO
0x963 RX_Frame_OctetsOK_63_32 RO

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