E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 12/13/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.12.2.26. Configuration for RX PLD Block

Offset: 0x355

Configuration for RX PLD Block Fields

Bit Name Description Access Reset
4 sel_50gx2 Select 50Gx2 mode
  • 0: Use 4 EMIB channels for data output
  • 1: Use 2 EMIB channels for data output
The RX datapath must be reset after changing this field.
  • Defaults to 0 after power up
  • After i_csr_rst_n, default value depends on the Select Ethernet Rate parameter
    • When Select Ethernet Rate = 100G, sel_50gx2 = 0
The RX datapath must be reset after changing this field.
RW 0x0
3 use_lane_ptp Select the input for the PTP channels

Valid for multilane EHIP (ehip_core) only

  • 0: PTP RX data comes from EHIP core
  • 1: PTP RX data comes from connected EHIP lanes
Default value after power up and i_csr_rst is 0
RW 0x0
2:0 rx_ehip_mode Select RX Port map

Selects how data from the EHIP is presented through the EMIB

  • 3'h0: MAC interface
  • 3'h1: MAC interface with PTP
  • 3'h2: PCS (MII) interface
  • 3'h3: PCS66 interface for OTN (forced descrambler bypass)
  • 3'h4: PCS66 interface (descrambler optional)
  • 3'h7: PMA direct interface
  • After power up, defaults to 0
  • After i_csr_rst_n, default depends on the Select Ethernet IP Layers parameter
    • When eSelect Ethernet IP Layers = MAC+PCS, rx_ehip_mode = 3'd0
    • When Select Ethernet IP Layers = PCS-only, rx_ehip_mode = 3'd2
    • When Select Ethernet IP Layers = FlexE PHY, rx_ehip_mode = 3'd4
    • When eSelect Ethernet IP Layers = OTN PHY, rx_ehip_mode = 3'd3
RW 0x0

Did you find the information on this page useful?

Characters remaining:

Feedback Message