E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 12/13/2021
Public

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Document Table of Contents

3.11.1. PHY Registers

Table 107.  PHY Registers
Address Bit Name Description Access Reset
0x310 5 set_data_lock Set data lock

1: Force PLL to lock to data.

RW 0x0
4 set_ref_lock Set ref lock

1: Force PLL to lock to reference.

RW 0x0
2 soft_rx_rst Soft RXP Reset

1: Resets the RX PCS and RX MAC.

RW 0x0
1 soft_tx_rst Soft TXP Reset

1: Resets the TX PCS and TX MAC.

RW 0x0
0 eio_sys_rst Ethernet IO System Reset

1: Resets the IP core (TX and RX MACs, Ethernet reconfiguration registers, PCS, and transceivers).

RW 0x0
0x321 3:0 eio_freq_lock Clock Data Recovery (CDR) PLL locked

1: Corresponding physical lane's CDR has locked to reference for 10 and 25G links.

RO 0x0
0x30E 9 use_aligner Use RX PCS Alignment

1:RX PCS has aligner turned on to align incoming data.

0: The RX PCS expects to receive aligned data, and its internal alignment logic is bypassed.

  • After power on, this register defaults to 0
  • After i_csr_rst_n, this register is set depending on the Select Ethernet IP Layers parameter
  • In all modes that include RS-FEC, this register is set to 0
  • In modes that do not include RS-FEC, this register is set to 1
RW 0x0
0x322 0 tx_pcs_ready TX Ready

1: TX Datapath is out of reset, stable, and ready for use.

RO 0x0
0x323 19:0 frmerr Frame error(s) detected

1: A frame error was detected on the corresponding lane.

  • For single lanes, only bit 0 is used
  • This bit is sticky, and must be cleared by asserting sclr_frame_error
RO 0x0
0x324 0 clr_frmerr Clear PHY frame error(s).

1: Return all sticky frame error bits to 0.

RW 0x0
0x325 19 rx_pcs_in_rst Reset RX PCS

1: Reset RX PCS.

  • Defaults to 0 after power-up and i_csr_rst_n asserted
RW 0x1
17 tx_pcs_in_rst Reset TX PCS

1: Reset TX PCS.

  • Defaults to 0 after power-up and i_csr_rst_n asserted.
RW 0x1
14 force_hip_ready Override Hard IP ready

1: Assert force_hip_ready, even if all the conditions for Hard IP ready have not been met.

  • Note that one of the conditions for force_hip_ready is the completion of configuration loading. If there is a problem with the configuration logic, force_hip_ready may be prevented from taking effect
  • This feature is provided for test and debug only
  • Defaults to 0 after power-up and i_csr_rst_n asserted.
RW 0x0
2 trst TX Datapath reset

1: Hold TX datapath in reset, including TX PLD, TX MAC, and TX PCS.

  • Performs same function as the i_tx_rst_n port
  • The IP core asserts o_tx_rst signal when this reset is active
  • Does not reset TX MAC statistics
  • Space the assertion and deassertion of reset to prevent sudden changes in power consumption
  • Defaults to 0 after power-up and i_csr_rst_n asserted.
RW 0x0
0 rrst RX Datapath reset

1: Hold RX datapath in reset, including RX PLD, RX MAC, and RX PCS.

  • Performs same function as the i_rx_rst_n port
  • The IP core asserts o_rx_rst when this reset is active
  • Does not reset RX MAC statistics
  • Space the assertion and deassertion of reset to prevent sudden changes in power consumption
  • Defaults to 1 after power-up
  • Defaults to 0 after i_csr_rst_n asserted.
RW 0x0
0x326 1 hi_ber Hi-BER

1: One or more virtual lanes are in Hi-BER state.

RO 0x0
0 rx_aligned RX PCS fully aligned

1: The RX PCS is fully aligned and ready to start decoding data

RO 0x0
0x32A 31:0 count BER Count
  • 32-bit count that increments each time the core enters BER_BAS_SH state.
  • Rolls over when maximum count is reached
  • Clears when the channel is reset
  • Can be captured using snapshot or RX shadow request
RO 0x0
0x32B 19:16 ehip_rx_transfer_ready EHIP/ELANE RX Channels Transfer Ready Status

1: transfer_ready is 1.

RO 0x0
3:0 ehip_tx_transfer_ready EHIP/ELANE TX Channels Transfer Ready Status

1: transfer_ready is 1.

RO 0x0
0x341 31:0 khz_rx Recovered clock frequency

Recovered clock frequency/100, in KHz.

RO 0x0
0x342 31:0 khz_tx TX clock frequency

TX clock frequency/100, in KHz.

RO 0x0
0x351 24 err_tx_avst_fifo_overflow TX AVST FIFO Overflow
  • Indicates that the FIFO was written while full
  • Overflow would never happen—if it does, this indicates a problem with the way i_valid is being driven
  • Once asserted this bit holds value until the i_clear_internal_error port is asserted to clear it
  • This bit doesn't need to be polled— the IP asserts o_internal_err signal if this signal goes high
RO 0x0
23 err_tx_avst_fifo_empty TX AVST FIFO ran empty unexpectedly
  • Asserts when the TX FIFO runs empty (regardless of read enable)
  • Does not apply when in MAC mode
  • Empty should never happen—if it does, this indicates a problem with the way i_valid is being driven
RO 0x1
22 err_tx_avst_fifo_underflow TX AVST FIFO Underflow
  • Indicates that the FIFO was read when empty after steady state reading was established
  • Underflow should never happen—if it does, this indicates a problem with the way i_valid is being driven
  • Once asserted this bit holds value until the i_clear_internal_error port is asserted to clear it, or the TX datapath is reset
  • This bit doesn't need to be polled—o_internal_err is asserted if this signal goes high
RO 0x0
0x360 20 use_hi_ber_monitor Enable Hi-BER Monitor

0: Turn off Hi-BER monitor

1: Turn on Hi-BER monitor
  • The Hi-BER monitor is turned on by default because it is used for standard compliance
  • Hi-BER is needed to support Auto-Negotiation, and is generally used to report poor link conditions
  • When the Hi-BER monitor is turned on, if a Hi-BER condition is detected, the PCS replaces incoming data with Local Fault blocks
  • Disable the Hi-BER monitor if you need to monitor RX data while in a Hi-BER state
  • At power-on, this register defaults to 0
  • After i_csr_rst_n is asserted, the register is set to the value given by the hi_ber_monitor module parameter
RW 0x0
0x37A 20:0 cycles Timer window for BER measurements

Sets the timer window for BER measurements in clock cycles.

The Ethernet Standard (IEEE 802.3) defines the required times for Hi-BER measurements for each rate. These times must be converted to clock cycles with the accuracy of within +1% and -25% of the specified times.
Note: If the clock rate you are using is different from the clock rate used to calculate the cycle count, you need to scale the cycle count.
  • 100GBASE-R4: 21'd201415 (from Clause 82, 0.5ms +1%,-25% at 402.3 MHz
  • 25GBASE-R1: 21'd806451 (from Clause 107, 2.0 ms +1%, -25% at 402.3 MHz
  • 10GBASE-R1: 21'd20141 (from Clause 49, 0.125ms +1%, -25% at 161.13 MHz
  • 10GBASE-R1: 21'd50403 (from Clause 49, 0.125ms +1%, -25% at 402.83 MHz

The RX PCS must be reset after changing this value.

RW 0x312C7
0x37B 6:0 count Hi-BER Frame Errors

Sets the BER count that triggers hi_ber.

The Ethernet Standard (IEEE 802.3) defines the appropriate setting for ber_invalid_count based on rate.
  • 100GBASE-R4: 7'd97 (from Clause 82)
  • 25GBASE-R1: 7'd97 (from Clause 107)
  • 10GBASE-R1: 7'd16 (from Clause 49)

The RX PCS must be reset after changing this value.

RW 0x61
0x37C 31:0 count Error block count
  • Counts the number of error blocks produced by the RX PCS decoder
  • Valid only when the RX PCS decoder is used and alignment is achieved
  • The error blocks can be received from the remote link, or generated by violations of the Ethernet Standard 64B66B encoding specification
  • The counter is 32-bit wide and rolls over when the max count is reached
  • The counter is reset when the RX datapath is reset, or the RX PCS is reset
RO 0x0

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