E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 12/13/2021
Public

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Document Table of Contents

2.12.5.38. RX Flow Control Feature Configuration

Offset: 0x709

RX Flow Control Feature Configuration Fields

Bit Name Description Access Reset
1 en_pfc Enable Priority Flow Control RX
1: Enable Priority Flow Control
  • After power-on, this reset is set to 0
  • After i_csr_rst_n, this register is set to a value given by the module parameter flow_control
RW 0x0
0 en_sfc Enable Standard Flow Control RX
1: Enable Standard Flow Control (link PAUSE)
  • After power-on, this reset is set to 0
  • After i_csr_rst_n, this register is set to a value given by the module parameter flow_control
RW 0x0

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