E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 12/13/2021
Public

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2.12.5.14. Higher 2 bytes of the Source address for Flow Control frames

Offset: 0x610

Higher 2 bytes of the Source address for Flow Control frames Fields

Bit Name Description Access Reset
15:0 saddrh Higher 2 bytes of the Flow control Source Address
Higher 2 bytes of the 6 byte source address used for SFC and PFC frames
  • At power-on, saddrh is set to 16'hE100
  • After i_csr_rst_n is asserted, saddrh is set to the value given by module parameter tx_pause_saddr[47:32]
RW 0xE100

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