E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 12/13/2021
Public

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2.9.1.6.1. Determining Link Fault Condition

In Intel® Quartus® Prime, the E-Tile Hard IP for Ethernet Intel FPGA IP provides the o_sl_rx_pcs_fully aligned/o_rx_pcs_fully aligned signal to determine link fault condition. Implement the following pseudo-code on the RX MII port:
If (o_sl_rx_pcs_fully aligned/o_rx_pcs_fully_aligned  == 0)  (

 •local fault pattern received on o_sl_rx_mii_d/o_rx_mii_d 

 •remote fault is expected on the TX serial data
)
else if (o_sl_rx_pcs_fully aligned/o_rx_pcs_fully_aligned   == 1 && o_sl_rx_mii_valid/o_rx_mii_valid==1)

  •o_sl_rx_mii_d/o_rx_mii_d is a valid XGMII block

else if (o_sl_rx_pcs_fully aligned/o_rx_pcs_fully_aligned   ==1 && o_sl_rx_mii_valid/o_rx_mii_valid==0)

 •Ignore o_sl_rx_mii_d/o_rx_mii_d as it is not valid XGMII data

endif

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