E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 12/13/2021
Public

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Document Table of Contents

2.12.2.11. PCS Error Injection

Offset: 0x327

PCS Error Injection Fields

Bit Name Description Access Reset
19:0 inj_err Inject Error

0->1: Flip bits to inject encoding errors in corresponding virtual lane

0 :Clear all error injection settings

  • For EHIP with rate set to 100G, bits 0 to 19 are valid, and correspond to virtual lanes 0...19
RW 0x0

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