E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 12/13/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.2. E-Tile CPRI PHY Intel® FPGA IP Overview

The E-Tile CPRI PHY Intel® FPGA IP block diagrams show the main blocks, and internal and external connections for each variant.
Figure 72.  E-Tile CPRI PHY IP Block Diagram
  • The E-Tile CPRI PHY IP core supports line bit rate of 2.4376, 3.0720, 4.9152, 6.144, 9.8304, 10.1376, 12.1651, and 24.33024 Gbps up to four channels. The RS-FEC block is optional for the IP core variations that target 10.1376, 12.1651, and 24.33024 Gbps CPRI line rate.
  • The soft reset sequencer implements the reset sequence of the IP core.
  • The IP variations with 2.4376, 3.0720, 4.9152, 6.144, and 9.8304 Gbps CPRI line rates include 8b/10b soft PCS and the IP variations that target CPRI line rates 10 .1376, 12.1651, and 24.33024 Gbps use 64b/66b hard PCS within the Native PHY.
  • It supports latency measurement for delay calculation between the FPGA pins to the core.
Note: You need to configure an E-tile Native PHY instance as a PLL that drives CPRI PHY's Embedded Multi-die Interconnect Bridge (EMIB) interface across all the channels. Refer to section Master-Slave Configuration: Option 2 to see how to configure E-tile Native PHY as a PLL. The E-Tile CPRI PHY IP does not support Master-Slave Configuration: Option 1

Did you find the information on this page useful?

Characters remaining:

Feedback Message