E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 12/11/2021
Public
Document Table of Contents

4.3.1.2. Reset

Nios® system controls the resets implemented in the design example via PIO. To reset the design under test (DUT) IP, always deassert the i_sl_csr_rst_n first before the sl_tx/rx_rst_n and i_reconfig_reset signals. When performing dynamic reconfiguration, i_sl_csr_rst_n and i_reconfig_reset should not be toggled.

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