E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 12/11/2021
Public
Document Table of Contents

4.4.6. Dynamic Reconfiguration Flow for 24G CPRI FEC to 24G CPRI Non-FEC

This section provides a sequential flow for dynamic reconfiguration of 24G CPRI FEC configuration to 24G CPRI Non-FEC configuration. For other variations, you can refer to the generated C file that provides comprehensive information through comments.
  1. Assert the i_sl_tx_rst_n and i_sl_rx_rst_n reset signals.
  2. Disable Serdes (via PMA attribute code 0x0001). For more information, refer to the E-Tile Transceiver PHY User Guide.
  3. Perform PMA Analog Reset. For more information, refer to the E-Tile Transceiver PHY User Guide.
  4. Change the following registers:
    Table 42.  Registers: 24G CPRI FEC to 24G CPRI Non-FEC
    Block Configuration Registers Offset Register Bits From Value To Value
    ELANE txmac_ehip_cfg 0x40B am_width [5:3] 3’b100 3’b001
    phy_ehip_pcs_modes 0x30E use_aligner [9] 1’b0 1’b1
    cpri_rate_sel 0xC00 - 1B B
    RS-FEC rsfec_top_clk_cfg 0x005 fec_lane_ena [3:0] 4’bxxx1 4’bxxx0
    rsfec_top_rx_cfg 0x014 core_rx_out_sel0 [1:0] 2’b01 2’b00
    Transceiver xcvrif_ctrl0 (0x4) 0x004 cfg_tx_data_in_sel [4:2] 2’b01 2’b00
    xcvrif_ctrl0 (0x5) 0x005 cfg_clk_en_fec_d2_tx [13] 1’b1 1’b0
    cfg_clk_en_pcs_d2_tx [12] 1’b0 1’b1
    xcvrif_ctrl0 (0x7) 0x007 cfg_rx_fifo_clk_sel [30:29] 2’b00 2’b10
    xcvrif_ctrl0 (0x37) 0x037 rxbit_cntr_pma [7] 1’b0 1’b1
    cfg_rx_bit_counter_rollover 0x036, 0x035, 0x034 - 13‘d5248 ('h1480) 13'd6304 (‘h18A0)
  5. Adjust the phase offset of a recovered clock using the RX Phase Slip (via PMA attribute code 0x000E). For more information, refer to the E-Tile Transceiver PHY User Guide.
  6. Enable Serdes (via PMA attribute code 0x0001). For more information, refer to the E-Tile Transceiver PHY User Guide.
  7. Enable internal serial loopback (via PMA attribute code 0x0008). For more information, refer to the E-Tile Transceiver PHY User Guide.
  8. Deassert the i_sl_tx_rst_n and i_sl_rx_rst_n reset signals.
  9. Wait until:
    PIO_OUT[3:0] = 0x7 (o_sl_rx_pcs_ready, o_sl_rx_block_lock, o_ehip_ready asserted)
  10. Clear ELANE statistic counters.
  11. Enable packet generator to start sending packets. Wait for 100us.
  12. Check for checker_pass status, wait until:
    PIO_OUT[4:0] = 0xF (checker_pass, o_sl_rx_pcs_ready, o_sl_rx_block_lock, o_ehip_ready asserted)
  13. Disable packet generator to stop sending packet.

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