E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

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ID 683860
Date 12/11/2021
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2.3.1.1. Non-PTP E-tile Ethernet IP for Intel Agilex FPGA 100GE MAC+PCS with Optional RS-FEC Simulation Design Example

The simulation block diagram below is generated using the following settings in the IP parameter editor:
  1. Under the IP tab:
    1. Single 100GE with optional RSFEC or 100GE or 1 to 4 channel 10GE/25GE with optional RSFEC and PTP as the core variant.
    2. 100GE Channel as Active channel(s) at startup if you choose 100GE or 1 to 4 channel 10GE/25GE with optional RSFEC and PTP as the core variant.
    3. Enable RSFEC to use the RS-FEC feature.
      Note: The RS-FEC feature is only available when you select 100GE or 1 to 4 channel 10GE/25GE with optional RSFEC and PTP as the core variant.
  2. Under the 100GE tab:
    1. 100G as the Ethernet rate.
    2. MAC+PCS as Select Ethernet IP Layers to use instantiate MAC and PCS layer or MAC+PCS+(528,514)RSFEC/MAC+PCS+(544,514)RSFEC to instantiate MAC and PCS with RS-FEC feature.
  3. Enable asynchronous adapter clocks to use the asynchronous adapter feature.
Figure 13. Simulation Block Diagram for E-tile Ethernet IP for Intel Agilex FPGA 100GE MAC+PCS with Optional RS-FEC Design Example
Note: If Enable asynchronous adapter clocks is enabled, the o_clk_div66 feeds the i_clk_tx and i_clk_rx clocks.

The testbench sends traffic through the IP core, exercising the transmit side and receive side of the IP core.

To speed up simulation, the IP core simulation model sends alignment marker tags at shorter intervals than required by the IEEE Ethernet standard. The standard specifies an alignment marker interval of 16,384 words in each virtual lane. The simulation model with the testbench implements an alignment marker interval of 512 words.

The successful test run displays output confirming the following behavior:

  1. The client logic resets the IP core.
  2. Waits for RX datapath to align.
  3. Once alignment is complete, client logic transmits a series of packets to the IP core.
  4. The client logic receives the same series of packets through RX MAC interface.
  5. The client logic then checks the number of packets received and verify that the data matches with the transmitted packets.
  6. Displaying Testbench complete.

The following sample output illustrates a successful simulation test run for a 100GE, MAC+PCS with optional RS-FEC IP core variation.

# o_tx_lanes_stable is 1 at time             345651500
# waiting for tx_dll_lock....
# TX DLL LOCK is 1 at time             398849563
# waiting for tx_transfer_ready....
# TX transfer ready is 1 at time             399169435
# waiting for rx_transfer_ready....
# RX transfer ready is 1 at time             410719813
# EHIP PLD Ready out is 1 at time             410776000
# EHIP reset out is 0 at time             411040000
# EHIP reset ack is 0 at time             412282101
# EHIP TX reset out is 0 at time             413160000
# EHIP TX reset ack is 0 at time             462643731
# waiting for EHIP Ready....
# EHIP READY is 1 at time             462750387
# EHIP RX reset out is 0 at time             463088000
# waiting for rx reset ack....
# EHIP RX reset ack is 0 at time             463283667
# Waiting for RX Block Lock
# EHIP RX Block Lock  is high at time             467376591
# Waiting for AM lock
# EHIP RX AM Lock  is high at time             468643131
# Waiting for RX alignment
# RX deskew locked
# RX lane aligmnent locked
# ** Sending Packet           1...
# ** Sending Packet           2...
# ** Sending Packet           3...
# ** Sending Packet           4...
# ** Sending Packet           5...
# ** Sending Packet           6...
# ** Sending Packet           7...
# ** Received Packet          1...
# ** Sending Packet           8...
# ** Received Packet          2...
# ** Sending Packet           9...
# ** Received Packet          3...
# ** Received Packet          4...
# ** Sending Packet          10...
# ** Received Packet          5...
# ** Received Packet          6...
# ** Received Packet          7...
# ** Received Packet          8...
# ** Received Packet          9...
# ** Received Packet         10...
# ====>MATCH!     ReaddataValid = 1 Readdata = 11112015 Expected_Readdata = 11112015 
# 
# ====> writedata = ffff0000 
# 
# ====>MATCH!     ReaddataValid = 1 Readdata = 11112015 Expected_Readdata = 11112015 
# 
# ====> writedata = 4321abcd 
# 
# ====>MATCH!     ReaddataValid = 1 Readdata = 4321abcd Expected_Readdata = 4321abcd 
# 
# ====> writedata = a5a51234 
# 
# ====>MATCH!     ReaddataValid = 1 Readdata = a5a51234 Expected_Readdata = a5a51234 
# 
# ====> writedata = abcda5a5 
# 
# ====>MATCH!     ReaddataValid = 1 Readdata = abcda5a5 Expected_Readdata = abcda5a5 
# 
# ====> writedata = 4321abcd 
# 
# ====>MATCH!     ReaddataValid = 1 Readdata = 4321abcd Expected_Readdata = 4321abcd 
# 
# ====> writedata = a5a51234 
# 
# ====>MATCH!     ReaddataValid = 1 Readdata = a5a51234 Expected_Readdata = a5a51234 
# 
# ====> writedata = abcda5a5 
# 
# ====>MATCH!     ReaddataValid = 1 Readdata = abcda5a5 Expected_Readdata = abcda5a5 
# 
# TX enabled
# **
# ** Testbench complete.
# **
# *****************************************

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