E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

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ID 683860
Date 12/11/2021
Public
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2.3.2.1. 100GE MAC+PCS with Optional RS-FEC and PMA Adaptation Flow Hardware Design Example Components

Figure 18. 100GE MAC+PCS with Optional RS-FEC Hardware Design Example High Level Block Diagram
The E-tile Ethernet IP for Intel Agilex FPGA hardware design example includes the following components:
  • E-tile Ethernet IP for Intel Agilex FPGA core. The IP core consists of 4 channels if you select (528,514) RS-FEC option, and 2 transceiver channels if you select (544,514) RS-FEC option and enabled asynchronous adapter.
  • Client logic that coordinates the programming of the IP core and packet generation.
  • IOPLL to generate a 100 MHz clock from a 50 MHz input clock to the hardware design example.
  • JTAG controller that communicates with the System Console. You communicate with the client logic through the System Console.

The hardware design example uses run_test command to initiate packet transmission from packet generator to the IP core. By default, the internal serial loopback is disabled in this design example. Use the loop_on command to enable the internal serial loopback. When you use the run_test or the run_test_pam4 commands to run the hardware test in the design examples, the script enables internal loopback. When the internal serial loopback is enabled, the IP core receives the packets and transmit to the packet generator. The client logic reads and print out the MAC statistic registers when the packet transmissions are complete.

The following sample output illustrates a successful hardware test run for 100GE, MAC+PCS with (528,514) RS-FEC variation:
% run_test
--- Turning off packet generation ----
--------------------------------------
--------- Enabling loopback ----------
--------------------------------------
--- Wait for RX clock to settle... ---
--------------------------------------
-------- Printing PHY status ---------
--------------------------------------
 RX PHY Register Access: Checking Clock Frequencies (KHz) 
	REFCLK 		:0 (KHZ) 
	TXCLK 		:40285  (KHZ) 
	RXCLK 		:40284  (KHZ) 
	TXRSCLK 	:0  (KHZ) 
	RXRSCLK 	:0  (KHZ) 
 RX PHY Status Polling 
 Rx Frequency Lock Status     0x0000000f 
 Mac Clock in OK Condition?   0x00000001 
 Rx Frame Error               0x00000000 
 Rx PHY Fully Aligned?        0x00000001 
 Rx AM LOCK Condition?        0x00000001 
 Rx Lanes Deskewed Condition? 0x00000001 
---- Clearing MAC stats counters -----
--------------------------------------
--------- Sending packets... ---------
--------------------------------------
----- Reading MAC stats counters -----
--------------------------------------

==========================================================================================
                        STATISTICS FOR BASE 0x000900 (Rx)                               
 ==========================================================================================
Fragmented Frames                : 0 
Jabbered Frames                  : 0 
Any Size with FCS Err Frame      : 0 
Right Size with FCS Err Fra      : 0 
Multicast data  Err Frames       : 0 
Broadcast data Err  Frames       : 0 
Unicast data Err  Frames         : 0 
Multicast control  Err Frame     : 0 
Broadcast control Err  Frame     : 0 
Unicast control Err  Frames      : 0 
Pause control Err  Frames        : 0 
64 Byte Frames                   : 7190 
65 - 127 Byte Frames             : 6965 
128 - 255 Byte Frames            : 14338 
256 - 511 Byte Frames            : 28779 
512 - 1023 Byte Frames           : 57548 
1024 - 1518 Byte Frames          : 55880 
1519 - MAX Byte Frames           : 0 
> MAX Byte Frames                : 1669560 
Rx Frame Starts                  : 1840260 
Multicast data  OK  Frame        : 0 
Broadcast data OK   Frame        : 0 
Unicast data OK   Frames         : 1836399 
Multicast Control Frames         : 0 
Broadcast Control Frames         : 0 
Unicast Control Frames           : 0 
Pause Control Frames             : 0 
 ==========================================================================================
                        STATISTICS FOR BASE 0x000800 (Tx)                               
 ==========================================================================================
Fragmented Frames                : 0 
Jabbered Frames                  : 0 
Any Size with FCS Err Frame      : 0
Right Size with FCS Err Fra      : 0 
Multicast data  Err Frames       : 0 
Broadcast data Err  Frames       : 0 
Unicast data Err  Frames         : 0 
Multicast control  Err Frame     : 0 
Broadcast control Err  Frame     : 0 
Unicast control Err  Frames      : 0 
Pause control Err  Frames        : 0 
64 Byte Frames                   : 7190 
65 - 127 Byte Frames             : 6965 
128 - 255 Byte Frames            : 14338 
256 - 511 Byte Frames            : 28779 
512 - 1023 Byte Frames           : 57548 
1024 - 1518 Byte Frames          : 55880 
1519 - MAX Byte Frames           : 0 
> MAX Byte Frames                : 1669560 
Tx Frame Starts                  : 1840260 
Multicast data  OK  Frame        : 0 
Broadcast data OK   Frame        : 0 
Unicast data OK   Frames         : 1836399 
Multicast Control Frames         : 0 
Broadcast Control Frames         : 0 
Unicast Control Frames           : 0 
Pause Control Frames             : 0
The following sample output illustrates a successful hardware test run for 100GE, MAC+PCS with (544,512) RS-FEC variation:
% run_test_pam4
--- Turning off packet generation ----
--------------------------------------
--------- Enabling loopback ----------
--------------------------------------
--- Performing PMA adaptation... ---
--------------------------------------
------------ Starting PMA Adaptation ------------ 
------- Checking PMA Adaptation Status------- 
------- PMA Adaptation Done for ch0x0 -------
------- PMA Adaptation Done for ch0x2 -------
------------ Applying TX and RX Reset ----------
 wait for phy lock=50, locked=1
--Iteration:0 - PMA Adaptaion is Successful--
--- Wait for RX clock to settle... ---
--------------------------------------
-------- Printing PHY status ---------
--------------------------------------
 RX PHY Register Access: Checking Clock Frequencies (KHz) 
	REFCLK 		:0 (KHZ) 
	TXCLK 		:41504  (KHZ) 
	RXCLK 		:41505  (KHZ) 
	TXRSCLK 	:0  (KHZ) 
	RXRSCLK 	:0  (KHZ) 
 RX PHY Status Polling 
 Rx Frequency Lock Status     0x0000000f 
 Mac Clock in OK Condition?   0x00000001 
 Rx Frame Error               0x00000000 
 Rx AM LOCK Condition?        0x00000001 
 Rx Lanes Deskewed Condition? 0x00000001 
---- Clearing MAC stats counters -----
--------------------------------------
--------- Sending packets... ---------
--------------------------------------
----- Reading MAC stats counters -----
--------------------------------------
 ==========================================================================================
                        STATISTICS FOR BASE 0x000900 (Rx)                               
 ==========================================================================================
Fragmented Frames                : 0 
Jabbered Frames                  : 0 
Any Size with FCS Err Frame      : 0 
Right Size with FCS Err Fra      : 0 
Multicast data  Err Frames       : 0 
Broadcast data Err  Frames       : 0 
Unicast data Err  Frames         : 0 
Multicast control  Err Frame     : 0 
Broadcast control Err  Frame     : 0 
Unicast control Err  Frames      : 0 
Pause control Err  Frames        : 0 
64 Byte Frames                   : 7114 
65 - 127 Byte Frames             : 6925 
128 - 255 Byte Frames            : 14418 
256 - 511 Byte Frames            : 28563 
512 - 1023 Byte Frames           : 57313
1024 - 1518 Byte Frames          : 56067 
1519 - MAX Byte Frames           : 0 
> MAX Byte Frames                : 1670068 
Rx Frame Starts                  : 1840468 
Multicast data  OK  Frame        : 0 
Broadcast data OK   Frame        : 0 
Unicast data OK   Frames         : 1836559 
Multicast Control Frames         : 0 
Broadcast Control Frames         : 0 
Unicast Control Frames           : 0 
Pause Control Frames             : 0 
 ==========================================================================================
                        STATISTICS FOR BASE 0x000800 (Tx)                               
 ==========================================================================================
Fragmented Frames                : 0 
Jabbered Frames                  : 0 
Any Size with FCS Err Frame      : 0 
Right Size with FCS Err Fra      : 0 
Multicast data  Err Frames       : 0 
Broadcast data Err  Frames       : 0 
Unicast data Err  Frames         : 0 
Multicast control  Err Frame     : 0 
Broadcast control Err  Frame     : 0 
Unicast control Err  Frames      : 0 
Pause control Err  Frames        : 0 
64 Byte Frames                   : 7114 
65 - 127 Byte Frames             : 6925 
128 - 255 Byte Frames            : 14418 
256 - 511 Byte Frames            : 28563 
512 - 1023 Byte Frames           : 57313 
1024 - 1518 Byte Frames          : 56067
1519 - MAX Byte Frames           : 0 
> MAX Byte Frames                : 1670068 
Tx Frame Starts                  : 1840468 
Multicast data  OK  Frame        : 0 
Broadcast data OK   Frame        : 0 
Unicast data OK   Frames         : 1836559 
Multicast Control Frames         : 0 
Broadcast Control Frames         : 0 
Unicast Control Frames           : 0
Pause Control Frames             : 0

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