E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 12/11/2021
Public

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2.1.6. Testing the E-tile Ethernet IP for Intel Agilex FPGA Hardware Design Example

After you compile the E-tile Ethernet IP for Intel Agilex FPGA core design example and configure it on your Intel® Agilex™ device, you can use the System Console to program the IP core and its embedded Native PHY IP core registers.

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